James Webb Telescope Issue - 24

Feature
Impacts of Low-Power Requirements on the LEMS HMS Design
during the window of time when the processor card
would be awake.
Seismometer data was prioritized to take up more space
in the flash, being stored multiple times per second, with
telemetry only being stored on the order of minutes.
An FPGA design challenge involved squeezing data into
flash as efficiently as possible to optimize the efficiency of
the utilized flash. Before being written into flash, ADC data
needed to be timestamped. After all, the seismometer and
telemetry data need a time associated with each sample
to be valuable data. Instead of timestamping each ADC
read, which would roughly double the number of bits
per sample, only the first sample in each page of flash is
timestamped, with the rest of the samples assumed to be
taken at the configured sample rate. This nearly halves the
time required to transmit the data to the processor.
VI. Summary
The methods by which power consumption was reduced
in LEMS offer a unique insight into how high-level
requirements propagate through the entire design, even
affecting design choices at the lowest level. The need to
allow power-hungry instruments to survive and operate
continuously on the moon necessitated the development
of the LEMS HMS. The need to reduce power within the
HMS as much as possible necessitated choosing lowpower
hardware and even impacted low-level FPGA design.
And, although this focuses on a deep dive into the LEMS
HMS, other components of LEMS could be given the
same treatment. Many hours of engineering back and forth
discussion, design, and testing were required to develop
LEMS from an idea into a working system, now a TRL-6
verified lunar payload.
REFERENCES
[1] https://www.nasa.gov/feature/nasa-releases-prism-call-forpotential-lunar-surface-investigations
[2]
https://www.microsemi.com/product-directory/fpgas/
1690-proasic3#proasic3
[3] https://www.microsemi.com/product-directory/rad-tolerantfpgas/1696-rt-proasic3
James
Olsen has been working as a computer engineer
specializing in FPGA design at NASA's
Goddard Space Flight Center for five
years. At Goddard, James has worked as
an FPGA designer on a data encoder/
decoder for the recently launched Laser
Communications Relay Demonstration
(LCRD), and on numerous research and
development efforts. His first experience
with digital design was as an undergraduate pursuing physics
at Adelphi University. He acquired a BS in physics from
Adelphi University and a BS and MS in electrical engineering
from Columbia University. His hobbies include playing the
piano and trumpet, and reading fantasy and
sci-fi novels.
THE BRIDGE

https://www.nasa.gov/feature/nasa-releases-prism-call-for-potential-lunar-surface-investigations https://www.nasa.gov/feature/nasa-releases-prism-call-for-potential-lunar-surface-investigations https://www.microsemi.com/product-directory/fpgas/1690-proasic3#proasic3 https://www.microsemi.com/product-directory/fpgas/1690-proasic3#proasic3 https://www.microsemi.com/product-directory/rad-tolerant-fpgas/1696-rt-proasic3 https://www.microsemi.com/product-directory/rad-tolerant-fpgas/1696-rt-proasic3 https://grad.tufts.edu/engineering-masters/

James Webb Telescope Issue

Table of Contents for the Digital Edition of James Webb Telescope Issue