filter specifications) between any input signal and the corresponding signal at the filter's output. As a generally applicable metric, we measure the HW complexity (or HW budget) of the filter in terms of the effective total number of full adders (FA) and number of flip-flops (FF) when they are all running at the same sampling rate as the input signal to the filter. (This means that if hardware is "reused" in a design, e.g., through clocking FAs and FFs at higher rates, then that reuse factor will be applied as a multiplier for the nominal hardware count when computing the effective total hardware complexity.) One reason for using the FA + FF "total complexity" assessment is that there are various examples in the literature where one can lower a design's full-adder count by increasing the flip-flop cost, or vice versa. Early presentations of such a "trade-off" can be found in prefilter-equalizer design approaches [18]-[22] and in filter-masking-based techniques [22]-[32] where the number of filter taps is reduced substantially by increasing the number of delays (registers) in a certain manner. The practical average FA-to-FF hardware complexity ratio of 1 is adopted in the present analysis, given that the average silicon area of both FA and FF, in a typical FIR filter synthesized with the TSMC 0.18 µm standard library [33], is approximately 69 µm2 [34]. In Section II, we briefly discuss the hardware complexity requirements for implementing FIR filters and we present a practical approach to derive a general bound for the minimum hardware budget (resources) required to realize a practical FIR filter, given a target performance specification. The derived bound yields important insights that are further illustrated in Sections II and III. Furthermore, to both verify the validity of the presented bound and also to examine how close the hardware complexities of various announced filter designs are, compared to such a limit, a few examples are presented in Section III using highly-cited filter designs that have been employed to benchmark a variety of FIR filter-design methods. We believe these examples and the presented outcomes provide valuable practical insights regarding both the current state of the achievements in filter design and also the potential margins for further improvement (reduction) in hardware complexity. II. An Upper Bound on the Remez Order of FIR Filters-A Practical Approach Given target lowpass or highpass FIR filter specifications [passband ripple (d p), stopband attenuation (d s), passband edge (~ p), and stopband edge (~ s)], a designer can easily compute the lowest order ^orderminh of the realizable FIR filter when it is designed based on the Parks- McClellan [12]-[13] variation of the Remez exchange algorithm [11]. This is also applicable to bandpass filters, 12 IEEE cIrcuIts ANd systEMs MAgAzINE with the caveat that for asymmetric bandpass filters the smaller transition bandwidth should be used as the width of the transition band (D~ = ~ s - ~ p) in estimating the required order of the FIR filter [35]. The resulting filter has ordermin registers and SA = a # ordermin structural adders where we define parameter a in (2) as a function of the type of the target filter since this influences the number of non-zero taps and hence the number of structural adders: a#' 1 1 - 1/ M for most FIR filters for Mth band FIR filters. (2) Given the above number of structural adders (SA) and the parameter a as defined in (2), the number of coefficients (multipliers) required by the filter is: multipliers = 1 + SA = 1 + a ordermin multipliers . a ordermin . (3) Let us consider that there are effectively on average K add operations needed to realize each multiplier. Then according to (3) the total number of Multiplier Adders (MA) is MA . K # a ordermin . (4) Notice that in the case of a linear-phase FIR filter, due to the filter's structural symmetry, the effective number of Multiplier Adders is halved: Effective MA . 0.5 # K # a ordermin . (5) We must now examine the wordlength of the signal since it directly affects the size of the filter's adders and registers. Assuming a signal wordlength [36], [46] of W + 1 bits (including sign bit), the maximum absolute value of the signal is 2 W and, assuming a conservative 2-bit peak-to-average power ratio margin, above the signal's RMS level, the resulting quantization noise power is (see Appendix 1) Quantization Noise Power = ^ 2 W -2 h-2 12 . (6) Given a target passband ripple (d p) and stopband attenuation (d s), the overall quantization noise at the output of the designed filter must be practically negligible compared to the minimum of d p and d s (in order to meet the target filter spec.) Assuming that the filter is properly designed, so that the total noise injected by the filter structure is indeed practically negligible, the filter's input and output wordlengths should be large enough to support the required resolution (in order to be able to realize both d p and d s ). Therefore, as a general practical fIrst quArtEr 2018

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