# IEEE Circuits and Systems Magazine - Q1 2018 - 13

```Appendix 1
[Further insight into the relations (6) and (7)]

less than the smallest ripple that we will realize. That's the

We assume the signal is quantized to W + 1 bits (including

first line of (7). Then, applying a base-2 log to this inequal-

sign bit). Then the largest absolute signal value is 2 W . We as-

ity, we obtain:

sume that clipping degradation is negligible if we "back off"

-2 ^W - 2 h # log 2 ^12/10h + 2 log 2 6min ^d p, d sh@ .

the signal RMS level four times (i.e., 2 bits). So it is at 2 W-2.
This back-off margin supports 16 times (12 dB) peak signal
power to average signal power (enough for most practical

Now, dividing both sides by -2 yields:
^W - 2 h \$ log 2 10/12 - log 2 6min ^d p, d s h@ .

applications). Thus our signal RMS is 2 W-2 and hence, signal
power is at ^2 W-2h2 . We know that the quantization noise is

uniformly distributed within [−0.5, +0.5], hence its power is

Hence (W + 1) - log 2 68@ \$ log 2 10/12 - log 2 6min ^d p, d sh@

1/12. Thus, the ratio of quantization noise power to desired

=> (W + 1) \$ log 2 [8 10/12 ] - log 2 [min (d p, d s)]

signal power is (1/12)/ ^2

h which is equivalent to eqn. (6).

W-2 2

=> ^W + 1h \$ log 2 67.3@ - log 2 6min ^d p, d sh@

For (7), we start from a practical perspective and we

set the normalized power of (6) to approximately 10 times

which is approximately the last line of eqn. (7).

(conservative) bound, the wordlength is set (see Appendix 1) so that the quantization noise power is limited to:

(7)

In a direct-form implementation of this FIR filter, samples
of the input signal with wordlength W + 1 bits enter the
filter and are buffered in ordermin registers which, according to (7), are realized with at least (W + 1) ordermin
flip-flops (FF). The adder tree requires a total of MA + SA
adders to compute the linear combination of all input
samples (W + 1 bits each). This translates to at least
(W + 1) (MA + SA) full adders (FA). In practice, the costs
of these additions are not identical; they vary [34], [37]
in an adder tree depending on the filter coefficient values
and the number of filter taps. This is illustrated in Fig. 2
[34] for the high-order sharp-transition-band FIR Filter
example of [53].
There have of course been many efficient techniques
developed in recent years to minimize the bitwidth of
multiplier-adder tree, to considerably less than that indicated by the raw partial sums (e.g., in Fig. 2). Further discussion of such techniques is beyond the scope of this
paper and we refer the interested reader to [34], [37]-
[40]. For the purpose of our practical approach, adopted
here to identify a generally applicable approximation of
the minimal hardware requirement (given a target filter
specification), the total hardware complexity, in terms
of the number of full adders and flip-flops, is therefore:
fIrst quArtEr 2018

(8)

Using (7) and (8) we conclude
FA + FF \$ - ^ MA + SA + orderminh log 2 ;

min ^d p, d s h
E.
7
(9)

Given that SA = a ordermin we can rewrite (9) as
FA + FF \$ -^ MA + ^1 + a h orderminh log 2 ;

min ^d p, d s h
E.
7
(10)

In the lowest complexity filter implementation scenario all coefficients are desired to be trivial (powers-of-two)

Width (bit)

(2 W -2) -2
(min (d p, d s)) 2
#
12
10
min (d p, d s)
approximately (W + 1) \$ -log 2 ;
E.
7
(

Total HW complexity def HW budget
= FA + FF \$ ^ MA + SA + orderminh^W + 1 h .

26
24
22
20
18
16
14
12
10
120

100

80
60
40
Number of Coefficient

Partial Sum

20

0

Coefficient Multiplier Output

Figure 2. bit width for the tapped-delay line signals of the
121-tap filter of [53] indicating that the partial sum increases
monotonically for half of the adder tree (from [34]).

IEEE cIrcuIts ANd systEMs MAgAzINE

13

```

# Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2018

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