# IEEE Circuits and Systems Magazine - Q1 2018 - 20

```Is there a practical definition for the entropy of an FIR filter? Should we
perhaps define the hardware complexity of an FIR filter on the basis
of the minimum number of transistors required?

questions as in the case of Example 1: How close can
a practical design get to this boundary? Does any potentially remaining marginal hardware improvement
beyond this point justify the required (potentially extensive) design efforts? We again believe that the Fig. 9
illustration should provide a valuable insight regarding
how efficient a filter structure can be in realizing this
order-62 filter.

Similar to the prior two cases, this order-120 filter is a
good example because several previous publications
have chosen to use this filter when presenting their own
filter design methods.
This filter, referred to as filter L1, was also examined
in [53] where the FIRGAM algorithm was introduced.
The transposed direct-form implementation using
the FIRGAM algorithm was compared there to three
alternative implementations: the design wherein coefficients are obtained using the Remez algorithm
[11]-[13], an LMS algorithm from [56], and the Partial
Mixed-Integer Linear Programming (PMILP) algorithm
of [54]-[55]. The corresponding hardware complexities
are reported in [53] using an 8-bit input signal (including sign bit). Given that a demanding 80-dB attenuation
is desired in the stopband of the input signal, this input should have at least a 15-bit wordlength (including the sign bit) in order to have the minimum level of

Example 3: Order-120 wideband highpass FIR filter [56]:
As a very high-order filter design example, we now consider a demanding highpass wideband FIR filter, one
that was originally introduced in [56]. It has the following specifications:
■ Passband edge ~ p = 0.8r rad.; Stopband edge
■ Ripple d p = 0.0058 (±0.05 dB); Attenuation d s =
0.0001 (80 dB);

Achievable Remez Order as a Function of FA + FF When Target min(δp, δs) = 0.001 (Attenuation = 60 dB)

1,000

1,500

2,500

3168

3319
CSD 1989 [45]

3090
FIRGAM 2008 [53]

PMILP 2002 [54], [55]

2991

2398

2112

1764

2,000

MILP Method 2011 [50]

40

2800
2825

45

Genetic Algorithm

50

Fully-Pipelined

55

Non-Pipelined

59

Fully-Pipelined

60

1568

Given a required min(δp, δs) = 0.001,
our analysis suggests that it is
70 practically unlikely to be able to
realize a direct-form FIR filter
that corresponds to the left of
65 the boundary.

Fig. 6
Non-Pipelined

Max Remez Order that Can Be Practically Realized

75

3,000

Total Number of Full Adders and Flip-Flops (Hardware Budget in Terms of FA + FF)
Figure 7. Highest attainable remez order (y-axis) of a practically realizable fIr filter based on the bound defined in (12) (using
a = 1), shown by the blue solid line, given a specific hardware budget in terms of total number of full adders and flip-flops (x-axis)
for the filter design case of min ^d p, d sh = 0.001 (Example 1). this plot predicts that when 60-db attenuation in stopband of the input
signal is required, achieving a remez order of higher than 59 is quite unlikely if total hardware budget is less than 1500 fA + ff.
20

IEEE cIrcuIts ANd systEMs MAgAzINE

fIrst quArtEr 2018

```

# Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2018

Contents
IEEE Circuits and Systems Magazine - Q1 2018 - Cover1
IEEE Circuits and Systems Magazine - Q1 2018 - Cover2
IEEE Circuits and Systems Magazine - Q1 2018 - Contents
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