# IEEE Circuits and Systems Magazine - Q1 2018 - 24

```2,000

Remez Coefficients 2008 [53]
8780

7917
8089
PMILP 2002 [54], [55]

60

LMS 1983 [45]

80

7549

100

FIRGAM 2008 [53]

120

6174

140

Fully-Pipelined

160

5685

Given a required min(δp, δs) = 0.0001,
our analysis suggests that it is
practically unlikely to be able to
realize a direct-form FIR filter
that corresponds to the left of
the bound (solid blue line).

180

Fig. 10
Non-Pipelined

Max Remez Order that Can Be Practically Realized

Achievable Remez Order as a Function of FA + FF When Target min(δp, δs) = 0.0001 (Attenuation = 80 dB)
200

3,000
4,000
5,000
6,000
7,000
8,000
Total Number of Full Adders and Flip-Flops (Hardware Budget in Terms of FA + FF)

9,000

Figure 11. Highest attainable remez order shown by blue solid line (y-axis) of a practically realizable fIr filter, given a specific
hardware budget based on the bound defined in (12) (with a = 1) in terms of the total number of full adders and flip-flops (x-axis)
for the case of min ^d p, d sh = 0.0001 (Example 3). this plot predicts that when 80-db attenuation in the stopband of the input signal is required, achieving a remez order of higher than 120 is quite unlikely if the total hardware budget is less than 3860 fA + ff.
the hardware complexities (fA + ff) of a number of published filter design methods [53]-[58] are also provided here (using15-bit
input signal wordlength) as discussed in Example 3.

Achievable Remez Order as a Function of FA + FF When Target min(δp, δs) = 0.01 (Attenuation = 40 dB)

3965

3650
3696
Trellis Algorithm 1999 [59]
Li SPT Algorithm 1993 [60]

110

Assuming 8-bit Input

3411

120

Given a required min(δp, δs) = 0.01,
our analysis suggests that it is
practically unlikely to be able to
realize a direct-form FIR filter
that corresponds to the left of
the bound.

FIRGAM 2008 [53]

100
90
80
70
60
50
1,000

1,500
2,000
2,500
3,000
3,500
Total Number of Full Adders and Flip-Flops (Hardware Budget in Terms of FA + FF)

Remez Coefficients 2008 [53]

Max Remez Order that Can Be Practically Realized

130

4,000

Figure 12. Highest attainable remez order shown by blue solid line (y-axis) of a practically realizable fIr filter, given a specific
hardware budget based on the bound defined in (12) (with a = 1) in terms of the total number of full adders and flip-flops (x-axis)
for the case of min ^d p, d sh = 0.01 (Example 4). this plot predicts that when 40-db attenuation in the stopband of the input signal
is required, achieving a remez order higher than 100 is quite unlikely if the total hardware budget is less than 1890 fA + ff.
24

IEEE cIrcuIts ANd systEMs MAgAzINE

fIrst quArtEr 2018

```

# Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2018

Contents
IEEE Circuits and Systems Magazine - Q1 2018 - Cover1
IEEE Circuits and Systems Magazine - Q1 2018 - Cover2
IEEE Circuits and Systems Magazine - Q1 2018 - Contents
IEEE Circuits and Systems Magazine - Q1 2018 - 2
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IEEE Circuits and Systems Magazine - Q1 2018 - 12
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IEEE Circuits and Systems Magazine - Q1 2018 - Cover3
IEEE Circuits and Systems Magazine - Q1 2018 - Cover4
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