IEEE Circuits and Systems Magazine - Q2 2020 - 15

G. Motivation for On-Chip Syntonistor
One of the key reasons for network's tendency of gradually-out-of-sync is the mismatch among the frequencies of local oscillators inside the nodes. Oscillator's
frequency is influenced by deterministic factors (temperature, aging, pressure, shock) and stochastic factors
(white noise, flicker noise, random noise and etc.). Practically speaking, frequency instability is usually categorized as short-term noise (jitter, higher than 10 Hz) and
long-term noise (wander, below 10 Hz) [31]-[33]. Shortterm noise impairs circuit operation. Its impact on clock
synchronization however can be ignored since shortterm noise is blocked by the circuits once the circuit is
appropriately constructed and functions correctly. In
other words, clock signal's spectral purity does not affect the performance of synchronization. Compared to
frequency variations caused by environmental factors,
frequency wander (a long-term and low-frequency phenomenon) is the leading cause of network's graduallyout-of-sync [34], [35].
Frequency wander is typically caused by systematic
reasons, such as manufacture imperfection and component aging. Atomic oscillator (Rubidium and Cesium)
has the highest frequency stability of 10 -11 to 10 -12
(x = 1 s). OCXO (oven-controlled crystal oscillator) is
next in line at +10 -10 to 10 -11. TCXO (temperature-controlled crystal oscillator) is in the range of +10 -8 to 10 -9
[36]-[37]. Those high-quality oscillators are expense and
usually only used as PRC at high stratum level. Regular
XO (crystal oscillator) has stability in the range of +10 -5
to 10 -6. It also has significant aging rate in the range of
tens of ppm per year [37]. When XO of such low stability
is used in communicating nodes as local clock (which is
the case for most of today's networks), some methods of
compensation is certainly desired.
As mentioned, PTP provides a method of syntonization to correct slave clock's rate. In current practice, this method is however implemented on logical
clock (i.e. time register), not on actual clock circuitry.
Therefore, it is not a true syntonization since physical

clock is not altered (the clock circuit is not touched).
Its performance is thus limited. Our goal is to create
a hardware based syntonization method. Our method mainly focuses on XO since it is the most popular
choice due to its low cost. For this reason, it is desirable to adopt a clock circuit having following features
as XO's companion.
■■ fine frequency granularity and fast frequency
switching
■■ frequency-tuning being done in a highly traceable
fashion (so that high-level processing unit can
change node's frequency precisely in real time)
■■ frequency adjustment being digitally performed
and in a fashion that is transparent to algorithm
(no extra computation-load and message-traffic
burdening the main processor)
■■ can be on-chip integrated into nodes with low cost
By providing this capability of directly adjusting
physical clock, it is believed that some difficult problems that cannot be efficiently dealt with at algorithm
level, such as the rate adjustment and the linear time
function, can be solved from a new perspective. This
can eventually lead to a higher precision and accuracy
in time synchronization. In next section, we will introduce a clock circuit of such kind: TAF-DPS. The XO plus
TAF-DPS (i.e. TAF-DPS Syntonistor), will be used in section IV for creating a method of hardware syntonization.
III. TAF-DPS Clock Circuit
A. Review of TAF-DPS Working Principle
	
	
	

T A = I $ T,

Figure 5 shows the principal idea of TAF-DPS frequency synthesizer. It is based on the Time-Average-Frequency (TAF) concept [18], [38]. From a base time unit

TAF-DPS
Base Unit ∆

TTAF = (1-r ) . TA + r . TB
(1- r )%

TA = I . ∆

Frequency
Control Word
F=I+r

TB = (I + 1) $ T (1)

TTAF = 1 = (1 - r) $ T A + r $ TB = (I + r) $ T = F $ T (2)
fs
= - dF 1 = - dF fs, dfs = - dF (3)
dfs = - dF
F FT
F
fs
F
F 2T

r%

TA

TB

TA

TB

Synthesized Clock Signal

TB = (I +1) . ∆ = TA +∆
Figure 5. TAF-DPS working principle.

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IEEE Circuits and Systems Magazine - Q2 2020

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