IEEE Circuits and Systems Magazine - Q1 2021 - 11

lack of generality, we consider the typical case b = 2),
the s bit denotes the sign, and p = log 2 P . The exponent can be computed from the integer and fractional
parts. This fixed-point format provides a range of numbers similar to the FP: this range is defined by the IT
bits, while the width F controls the precision. The logarithmic representation may be beneficial to applications
with data and/or parameters that follow nonuniform distributions, such as the Convolutional Neural Networks
(CNNs), as described in Section IV-A.
With LNS, operations with higher complexity, such
as multiplication, division, square and square root,
are easily performed by applying fixed-point addition, subtraction, and left/right bit-shift, respectively.
Considering unsigned operands P and Q, represented
in LNS as p = log 2 P and q = log 2 Q, and BitShift(x, z),
regarded as the left-shifted value of x by an integer
z in fixed-point arithmetic, these operations are formulated in (1).
log 2 (P ) Q ) = p + q;
log 2 (P/Q ) = p - q;
log 2 (P 2 ) = 2 ) p = BitShift ( p, 1);
log 2 ( P ) = 1 ) p = BitShift ( p, -1) .
2

(1)

This simple logarithmic arithmetic comes at the cost
of more complex additions and subtractions, which map
in nonlinear operations. For two unsigned numbers
P and Q (the sign can be handled in parallel), addition
and subtraction can be calculated using Lemma 1.
Lemma 1
For (P, Q ) ! N, and with Max as the function that returns
the maximum value of a tuple of numbers, the following
formulation can be adopted to compute addition and subtraction in the LNS domain ^log 2 (P ! Q ) h:
log 2 ^ P ! Q h = Max ^ p, q h + log 2 ^1 ! 2 - p - q h

Note that the addition and subtraction operations
employ the Gaussian logarithms represented in (6) and
in Fig. 4.
G = log 2 ^1 ! 2 m h,

m=- q- p

(6)

For a modest number of bits, typically up to 20, the
functions in Fig. 4 can be implemented through lookup
tables [13]. However, given that the table size increases
burden of storing large tables in memory, such as bipartite tables and multipartite methods [14].
For a large number of bits, for example, 32 bits (Fig. I)
or even 64 bits, a piecewise polynomial approximation
[15] or the digit-serial methods [17], [18] can be used to
implement LNS addition/subtraction. Digit-serial methods, also known as iterative methods, calculate the result digit by digit. Similarly to the COordinate Rotation
DIgital Computer (CORDIC) method [16], an iterative
algorithm can approximate the exponential and logarithmic computation with sequences of digit-serial computations [17]. Signed-digit arithmetic was proposed to
simplify the exponential computation and reduce the
number of pipeline stages required for LNS addition/
subtraction [18]. Although the digit-serial methods require a low circuit area, they exhibit high latency.
The alternative piecewise polynomial approximation
methods provide a trade-off between performance and
cost. Linear Taylor interpolation has been used to implement 20-bit and 32-bit LNS Arithmetic Units (AUs) by applying a table-based error correction scheme to achieve
a similar accuracy to that of their FP counterparts [19].
Although a first-order interpolation is used, the error

4

(2)

Proof. For P \$ Q, addition and subtraction can be calculated using (3):
Q
log 2 (P ! Q ) = log 2 c P c 1 ! mm = p + log 2 ^1 ! 2 q - p h (3)
P

2
0
-2

while for P < Q:
log 2 ^Q ! P h = log 2 c Q c 1 ! P mm = q + log 2 ^1 ! 2 p - q h
Q

-4
-6

By combining (3) and (4):
log 2 ^ P ! Q h = Max ^ p, q h + log 2 ^1 ! 2 - p - q h
and Lemma 1 is proved.
FIRST QUARTER 2021

log2 (1 + 2λ)
log2 (1 - 2λ)

(4)

(5)
Y

-4

-2
(λ)

0

2

Figure 4. Plot of the functions log 2 (1 + 2 m) and log 2 (1 - 2 m)
(the latter has a singularity when m " 0).

IEEE CIRCUITS AND SYSTEMS MAGAZINE

11

IEEE Circuits and Systems Magazine - Q1 2021

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