# IEEE Circuits and Systems Magazine - Q1 2021 - 27

```I0
w0

n

+

I1
w1
rnd
wrnd

n

+

n

Comparator
(≥0)

+

Out

Accumulator

+
Leak

Figure 17. Simplified processing element using SC [78]: w i represent the factor associated to the I i inputs; w rnd represents the
weight associated to the noise source.

unconstrained, the system fluctuates among all possible
valid states. A logic value of '0' is assigned to m i (t ) = -1,
and '1' is assigned to m i (t ) = 1.
m i ^t + Tt h = sgn ^rnd ^-1, +1 h + tanh ^ I i ^t + Tt hhh
I i ^t + Tt h = I 0 c h i + / J ij m j ^ t hm
j

0

A

C0

-1
h1

0

h4

+2

(38)

The values of h and J for the AND gate are shown in
Fig. 16(b). The h vector elements correspond to the bias
weights close to the node in the graph (in the order h 0
for A, h 1 for B, and h 2 for Y ) (16(a)). Matrix J, which,
as expected, is symmetric, represents the weight of the
bidirectional connections, following also the order A,
B, Y. The gate is invertible; thus, for example, when Y is
clamped to 1, the only valid state is ^ A = 1, B = 1 h .
The organization of the nodes, which operate in
parallel, and their type, simple processing elements
with binary inputs and outputs, make Boltzmann machines well suited for the SC nonconventional arithmetic discussed in the previous section [78]. In Fig. 17,
an FSM state, as shown in Fig. 10, is stored as the accumulator: for the highest state of the FSM ^ S N - 1 h, a
positive input will not cause any increase in the value
stored in the accumulator; the inverse also holds true
for negative input signals and the lowest state. The
scaling values in (38) are included in the weight w i
terms in Fig. 17.
SC can be used to implement arithmetic functions
based on Boltzmann machines. A graph of the Boltzmann
machine for an invertible 1-bit FA is represented in Fig. 18;
A, B and C i are the inputs, and C o and S are the outputs
of the 1-bit FA [78]. In this case, the h vector elements in
Fig. 18(b) are all zero. The symmetric matrix J follows
the order A, B, C i, S, C o . Invertible multipliers can also
be implemented, which can be used for factorization. A
5-by-5-bit optimized invertible multiplier/divider/factorFIRST QUARTER 2021

h0
0

+2
-1

B

J

+1

+1
+2

-2

-1

S

+1

0

Ci

h3

0
h2
(a)
h=

0

0
-1
J = -1
+1
+2

0
-1
0
-1
+1
+2

0

0
-1
-1
0
+1
+2

0
+1
+1
+1
0
-2

+2
+2
+2
-2
0

(b)
Figure 18. Boltzmann Machine structure for the 1-bit FA [78]:
five nodes, those denoted A, B, C i refer to binary inputs,
and S and C o the outputs. (a) Boltzmann structure. (b) h and
J (38).

izer implemented in CMOS with the TSMC 65~nm process occupies 53, 818 n m 2, which is 13 times the area of
the conventional binary logic counterparts [78]. For the
latency, the convergence cycles are different depending
IEEE CIRCUITS AND SYSTEMS MAGAZINE

27

```

# IEEE Circuits and Systems Magazine - Q1 2021

## Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2021

Contents
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