IEEE Circuits and Systems Magazine - Q2 2022 - 19

population and time. The neuron model allows for four leak
modes that bias the internal state dynamics in four different
ways so that neurons can have radically different responses
to identical inputs. The leaks can be either positive
or negative to let the membrane potential to diverge from
or converge towards a resting potential. The neuron model
also provides two types of threshold; deterministic and stochastic,
so that neurons can fire at different patterns even
with the same accumulated membrane potential. It has six
reset modes to determine the membrane potential after firing,
enabling a rich finite-state transition behavior. To reduce
complexity, it adopts fixed-point arithmetic and the neuron
model uses only simple addition and multiplexing arithmetic/logic
units instead of complex function units such as multiplication,
division, and exponentiation.
The synapses themselves are binary (1: connected, 0:
disconnected). Each synapse connected to a neuron in the
crossbar is allocated a choice of four 8-bit signed weights.
The synapses of TrueNorth neurons are non-plastic, i.e. the
synaptic weight cannot be modified during the runtime.
Exploiting the provided configurability, users can use
TrueNorth neurons to implement a wide variety of computational
functions, including arithmetic, control, data
generation, logic, memory, classic neuron behaviors,
signal processing, and probabilistic computations. The
programmable leakage and threshold give neurons the capacity
to support a variety of neural codes including rate,
population, binary, and time-to-spike coding. Rich and
diverse array of complex computations and behaviors
can also be synthesized by composing multiple neurons
together. For example, the 20 behaviors of the Izhikevich
dynamical neuron model can be qualitatively replicated,
using a small number of elementary neurons.
A TrueNorth chip, built in Samsung's 28-nm process
technology, occupies 4.3 cm2 area and contains 5.4 billion
transistors. Each core has 104,448 bits of local memory to
store synapse states, neuron states and parameters, destination
addresses, and axonal delays. In total, the TrueNorth
has 428 million bits of on-chip memory. Addititionally, TrueNorth's
power density is 20 mW per cm2 which is highly efficient
in comparison to typical CPU's 50 to 100 w per cm2.
The very high energy efficiency of the TrueNorth processor
does not only come from the low-cost hardware
and simplified function, but also from its mixed synchronous-asynchronous
neuron architecture, which reduces
the neuron switching activities by 99%.The average firing
frequency of TrueNorth neurons is approximately 20 Hz,
which is close to the frequency of the Beta Wave associated
to normal waking consciousness. This activity is very
sparse compared to the speed of modern silicon. Joined
with extensive power-gating, event-driven computing and
asynchronous communication, the sparse activity significantly
improves the energy efficiency.
SECOND QUARTER 2022
2) Architecture and Communication
Multiple neurosynaptic cores are connected using distributed
on- and off-chip connectivity to construct complex
networks. There is no global clock other than a 1-kHz
global synchronization signal, which discretizes the neuron
dynamics into 1-ms time steps and ensures one-to-one
equivalence between software and hardware.
A two-dimensional mesh network of routers form the
backbone for interconnecting the 64x64 core array. Each
of the routers have five ports (north, south, east, west,
and local) and communicates spike event between cores
in a time-multiplexed manner. With this mesh network, a
neuron can talk to an axon on any core. When a neuron
spikes in a core, it looks up an axonal delay (4 bits) and
the destination address (8-bit absolute address for the
target axon and two 9-bit relative addresses representing
core hops in each dimension to the target core) in
the local memory and encodes it in a packet. This packet
is injected into the mesh, where it hops from core to
core-first in the x dimension then in the y dimension
(deadlock-free dimension-order routing). The asynchronous
router delivers spikes at 0.3 fJ per bit per
merge-split structure is used at the four edges of the
Active Synapse
Synaptic
Crossbar
nm . A
256 Neurons
(a)
(b)
Figure 10. Truenorth architecture (a) Functional view (b) A
corelet [138].
IEEE CIRCUITS AND SYSTEMS MAGAZINE
19
Input Connector
256 Axons
Output Connector

IEEE Circuits and Systems Magazine - Q2 2022

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