IEEE Circuits and Systems Magazine - Q2 2022 - 23

wafer, repeaters are required for signal and timing restoration.
Repeaters are placed at the boundaries of each
chip. Each repeater consists of a receiver, timing restoration
circuit and driver [283]. The packet-based inter-wafer
or wafer-to-host communication (i.e. Layer-2) is implemented
by dynamic routing chips connected to the wafer
surface [178].
4) Supporting Software/Software Ecosystem
BrainScaleS supports PyNN as programming interface.
A user can specify the parameters of neurons and define
connections and network topology by Python [284],
[285]. The existing packages in the PyNN ecosystem can
also be used with BrainScales [286].
D. Neuromorphic Super Computing
Platform: SpiNNaker
The spiking neural network architecture (SpiNNaker)
project is a massively parallel computer system based on
general purpose ARM processor, aimed at providing high
performance and flexible simulators for neuroscience experiments.
Its goal is to simulate up to a billion neurons
in real time [122].
1) Hardware Platform
The basic building block of the system is the SpiNNaker
chip. A SpiNNaker chip is a custom designed multiprocessor
system-on-chip, consisting 18 identical ARM968E-S
32-bit processors clocked at 200 MHz [128]. Each core has
32-kB instruction memory and 64-kB data memory. An offdie
128 MB SDRAM is stacked on the chip [118]. The chip
adopts a Globally Asynchronous Locally Synchronous
(GALS) architecture. Each core resides in its own clock
domain [287].
SpiNNaker chips are mounted on a printed circuit
board (PCB), forming a 48-node hexagonal array. A full
system can have up to 1200 such boards, resulting in 57K
nodes, 1M ARM cores and 7 T bytes of RAM in the entire
system [122], [128].
SpiNNaker consists of two different types of networks
at different hierarchies. The first one at the lower level is
the system NoC, which handles communication inside a
chip. The system NoC uses AMBA5 AXI interfaces [287]. It
connects the ARM cores and several slave devices, such
as system controller, Ethernet media-independent interface
controller, off-chip SDRAM etc. [128].
The second is the communication NoC, which is a
packet switching fabric responsible for system-wide
communications. It transmits packets from one processor
to any other processor, which doesn't have to be in
the same chip. The Router has six full-duplex links connecting
to adjacent chips of directions (North, Northeast,
East, South, Southwest, West) to form a 2-D trianguSECOND
QUARTER 2022
lar toroidal mesh. In addition, the system configuration
and information are also transmitted by communication
NoC [128], [287].
2) Neuron Models
SpiNNaker is based on a general purpose CPU, it has
higher flexibility than BrainScaleS. The project provides
a C-based event-driven programming model: SpiNNaker
Application Run-Time Kernel (ARK) and Application
Programming Interface (API). The programming model
enables modelling of arbitrary neuron and synapse
dynamics [132].
Users can write C functions (also called " callbacks " ) to
define a particular task, and then register the function to
scheduler specific events, so that the function can be triggered
by the event. The events can be arrival of a packet,
the completion of a DMA transfer, timer etc. [118], [132].
For example, [132] implemented the Izhikevich neuron
model and three different synapse models, i.e. currentbased
instantaneous spike response model, current- and
conductance-based models with first-order response.
[288] implemented a leaky integrate and fire model. [289]
Implemented stochastic neuron models on SpiNNaker,
and [290] provided implementation of current-based
leaky integrate and fire neurons and Izhikevich neurons.
3) Supporting Software/Software Ecosystem
SpiNNaker has a relatively well-developed software ecosystem
compared with other neuromorphic systems. In addition
to the basic SpiNNaker API, [248] introduced the PArtitioning
and Configuration MANager (PACMAN), which is
an intermediate translation layer that decouples the model
from SpiNNaker hardware, such that arbitrary neuron and
synapse dynamics, and arbitrary network topologies can
be implemented on the SpiNNaker system. Various frontend
programming libraries are built upon PACMAN to support
SpiNNaker including PyNN [291], Nengo [292], NEST
[293], Brian [294], [295], sPyNNaker [290] etc.
E. ANN-SNN Hybrid Design: Tianjic
Tianjic [296] is a 28 nm reconfigurable chip designed by
Tsinghua University. It provides a hybrid and synergistic
platform for both the Spiking Neural Network model
and the Artificial Neural Network Model. The Tianjic chip
contains around 40,000 neurons and 10 million synapses.
Tianjic's flexible reconfiguration enable this chip to
implement most neural networks (fully connected, convolutional,
pooling, spiking, etc.) from the same basic
topological layer.
1) SNN Models
Tianjic supports various neural network algorithms,
for the neuromorphic approach, it adopts the Spiking
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