IEEE Circuits and Systems Magazine - Q4 2022 - 1

Circuits
and Systems
IEEE
MAGAZINE
Volume 22, Number 4
Fourth Quarter 2022
Features
6 Wideband Beamforming With Rainbow Beam
Training Using Reconfigurable True-Time-Delay
Arrays for Millimeter-Wave Wireless
Chung-Ching Lin, Veljko Boljanovic, Han Yan, Erfan Ghaderi, Mohammad Ali Mokri,
Jayce Jeron Gaddis, Aditya Wadaskar, Chase Puglisi, Soumen Mohapatra, Qiuyan Xu,
Sreeni Poolakkal, Deukhyoun Heo, Subhanshu Gupta, and Danijela Cabric
The decadal research in integrated true-time-delay arrays have seen organic growth
enabling realization of wideband beamformers for large arrays with wide aperture widths.
This article introduces highly reconfigurable delay elements implementable at analog
or digital baseband that enables multiple Spatial Signal Processing (SSP) functions
including wideband beamforming, wideband interference cancellation, and fast beam
training. Details of the beam-training algorithm, system design considerations, system
architecture and circuits with large delay range-to-resolution ratios are presented leveraging
integrated delay compensation techniques. The article lays out the framework for truetime-delay
based arrays in next-generation network infrastructure supporting 3D beam
training in planar arrays, low latency massive multiple access, and emerging wireless
communications standards.
26 On the Accuracy of Analog Neural Network
©LES TODD, DUKE PHOTOGRAPHY
Inference Accelerators
T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar,
Prashant Saxena, Vineet Agrawal, Sapan Agarwal, and Matthew J. Marinella
Specialized accelerators have recently garnered attention as a method to reduce
the power consumption of neural network inference. A promising category of accelerators
utilizes nonvolatile memory arrays to both store weights and perform in situ
analog computation inside the array. While prior work has explored the design space
of analog accelerators to optimize performance and energy efficiency, there is seldom
a rigorous evaluation of the accuracy of these accelerators. This work shows
how architectural design decisions, particularly in mapping neural network parameters
to analog memory cells, influence inference accuracy. When evaluated using
ResNet50 on ImageNet,
the resilience of
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the system to analog non-idealities-cell
programming errors, analog-to-digital converter resolution, and array parasitic resistancesall
improve when analog quantities in the hardware are made proportional to the weights
in the network. Moreover, contrary to the assumptions of prior work, nearly equivalent
resilience to cell imprecision can be achieved by fully storing weights as analog quantities,
rather than spreading weight bits across multiple devices, often referred to as bit slicing.
By exploiting proportionality, analog system designers have the freedom to match the precision
of the hardware to the needs of the algorithm, rather than attempting to guarantee
the same level of precision in the intermediate results as an equivalent digital accelerator.
This ultimately results in an analog accelerator that is more accurate, more robust to analog
errors, and more energy-efficient.

IEEE Circuits and Systems Magazine - Q4 2022

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