IEEE Consumer Electronics Magazine - November/December 2020 - 78

Consumer Electronics Security

Figure 5. (a) and (b) Interdie or intradie variations in device parameters and their effect on the average
transient current that can mask the effect of a Trojan circuit. (c) Application of TeSR by iterating the original
FSM through multiple test trials to produce comparable side-channel signatures from the same IC.

Researchers have shown the feasibility of using
power,14 delay,17 temperature,18 and electromagnetic (EM) radiation19 as potential side-channel
parameters. However, obtaining the Trojan-free
or golden signature is a challenging task as it
requires destructive reverse engineering to
obtain a set of golden ICs from a batch of
untrusted ICs. The other challenge is the impact
of process variation introduced by manufacturing imperfections during IC fabrication. For the
same set of input vectors, the side-channel signature of two identical ICs could slightly vary due
to process variations. For instance, performing
the same operation in two identical microprocessors would consume slightly different power.
As shown in Figure 5(a), there exist two forms of
process variations: chip-to-chip and within the
chip. While chip-to-chip or interdie variation
introduces side-channel discrepancies among
two identical ICs, within the chip or intradie variation causes identical modules within the same
IC to have different side-channel characteristics.
As shown in Figure 5(b), this small difference
due to the process variation could be enough to
mask the Trojan's impact.
Temporal self-referencing (TeSR) method
compares multiple current signatures of the
same suspect IC obtained during multiple comparable time windows to evade the requirement
of golden ICs and the impact of process variation.14 As the original finite state machine (FSM)
of the circuit iterates through an identical set of
state transitions, internal circuit activity at each
iteration is expected to be the same unless there
is a sequential Trojan that is unable to iterate
with the original FSM. This situation is illustrated
in Figure 5(c), where the original circuit FSM is

looping through the same set of transitions during multiple test trials, whereas the Trojan FSM
goes through a different set of states in each
trial. Due to the difference in Trojan FSM's state
transitions in two comparable time windows
(test trials), the current signatures obtained during these two periods differ. TeSR eliminates the
need for a golden IC by comparing the signatures
of the same suspect IC at two different time windows. Hence, it also eliminates the impact of all
forms of process variations as the same set of
gates within the same IC is being operated at
two comparable iterations. However, this technique is only applicable to sequential Trojan
circuits.
Elimination of the golden IC requirement is
also possible while observing EM20 and light
emission19 as side-channel parameters. The simulation of the golden design augmented with
additional data from its layout can be used to
construct a model of the reference side-channel
signature. However, the detection accuracy is
limited by the discrepancies that may exist
between the simulation-based modeling of side
channel and actual silicon that suffer from process-induced variations. None of the above
golden IC free detection techniques can be
directly applied to COTS components as almost
all of them require the Trojan-free version of the
design in the form of layout or netlist for either
simulation or test generation purposes.
Verification of IP Trust
IP trust verification methods apply to a threat
model where an IP consumer intends to detect
Trojans in an untrusted hardware design obtained
from a 3PIP vendor. Unlike IC trust verification, in

IEEE Consumer Electronics Magazine

IEEE Consumer Electronics Magazine - November/December 2020

Table of Contents for the Digital Edition of IEEE Consumer Electronics Magazine - November/December 2020