IEEE Solid-States Circuits Magazine - Fall 2020 - 12

VB
VB
VA
VA

0.8
0.6
Voltage (V)

clock period, we say the circuit is
" metastable " [Figure 11(a)]. During
metastability, the indefinite nature of the comparator outputs can
propagate to the subsequent logic,
introducing large errors. This issue
becomes particularly serious in digital communication systems where
the error rate must be extremely
low, e.g., <10 -14 .
In the StrongArm latch of Figure 4, M5 and M 6 serve as the primary amplifying circuit during a
metastable state. From the model
shown in Figure 11(b), we can prove
that the positive feedback around
the loop is characterized by

0.4
0.2
0
110

120

130

140

150

Time (ps)
FIGURE 10: The RS latch outputs for the original and modified designs.

VDD

VXY0

VY
VX

CX
TCK

M6
X

2
(a)

(b)

The RS latch's delay proves critical in some ADC architectures and
must be minimized. Since the latch
operates by pulling one output low,
we surmise that M11 and M12 must
be relatively wide. Moreover, if we
increase the width of the inverters' PMOS devices, their outputs
rise with less delay. We then change
W 11, 12 to 800 nm and also the inverters' PMOS widths to 800 nm. As
shown in Figure 10, the total delay
now drops by 6 ps. The overall comparator circuit draws approximately
0.2 mW at 5 GHz.

to-peak swing of 2A 0 with a uniform
distribution, then the probability
that the difference (positive or negative) presented to the comparator is
less than DV is equal to DV/A 0 .
Upon sensing a small difference,
a comparator takes some time to
generate a well-defined logical output. If it cannot do so in half of the

∆V
∆V
α

Metastability
In an ADC environment, a comparator senses a random signal at the
moment it is clocked. Thus, its input
difference can be arbitrarily small.
For example, if the signal has a peak-

FA L L 2 0 2 0

where VXY0 denotes the initial value,
and the regeneration time constant,
x reg, is given by g m5, 6 /C X . Note that
this expression is valid only after the
initial fall of VX and V Y . If VXY is not
large enough after TCK /2 seconds to
write a well-defined state onto the
RS latch, an error can occur. Denoting the minimum acceptable value
of VXY by V1, we require that

FIGURE 11: (a) Comparator metastability and (b) the behavior of PMOS transistors during
this period.

τreg In α

FIGURE 12: A shift of regeneration response for different initial conditions.

IEEE SOLID-STATE CIRCUITS MAGAZINE

VXY0 $ V1 exp

- TCK /2
.(3)
x reg

Input differences that yield a VXY0 less
than this value cause a metastability
error. The error rate is therefore proportional to exp [- TCK / (2x reg)], underscoring the high impact of x reg .
We can compute x reg by measuring g m5, 6 and CX in Figure 4. Alternatively, we can obtain x reg directly
from simulations. Consider the two
regeneration scenarios depicted in
Figure 12, where VXY0 is chosen equal
to some amount, DV, or a smaller
amount, DV/a. We denote VX - VY
for the two cases by VXY1 and VXY2, respectively, and write from (2)
VXY 2 = DV exp t (4)
a
x reg
=
D
V
exp
(
ln a) exp t (5)

x reg

VXY = VXY0 exp t , (2)
x reg

= DV exp

t - x reg ln a
.(6)
x reg

Interestingly, VXY2 is simply equal
to VXY1 but shifted by x reg ln a. For
the design in Figure 4, we select an

IEEE Solid-States Circuits Magazine - Fall 2020

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