IEEE Solid-States Circuits Magazine - Fall 2020 - 21

core to core, due to increasingly complex functionalities and systems. Figure 1(b) presents the input-output
(I/O) bandwidth and I/O pin number
evolution through time [5], [6]. The
I/O bandwidth increases by approximately 2× every two years or 10×
every five years, while the I/O pin
number grows at a much smaller
rate, 1.7× every five years, because
of process and mechanical constraints. This results in a widening
gap between I/O bandwidth requirements and capabilities, notoriously
named the interconnect gap, which
has been a major and long-standing
challenge for more than a decade.
For the interconnect, the bandwidth density, defined as gigabits per
second per square micrometer, and
energy efficiency, defined as picojoules per bit, are the two critical performance metrics. In addition, bit
error rate (BER), latency, cost, and scalability with process development are
also important to support sustainable
increasing interconnect bandwidth
requirements. Energy efficiency is
determined by factors including signal
generation and processing effectiveness, baseband/digital signal processing (DSP) complexity and power
consumption, channel loss, receiver
sensitivity, and so on. Bandwidth
density is governed by factors such
as the active component bandwidth,
channel capacity, size and pitch, and
system form factor. The BER is established by the signal-to-noise ratio (SNR),

(a)

component and channel dispersion,
pre/postprocessing complexity and
capabilities, and so forth. Latency is
affected by the component response
and processing time and the time
of flight through channels. Cost is
governed by initial manufacturi ng expenses, yields, reliability,
pr o duc t l ife sp a n s , a n d r e l ate d
factors. These challenges have in--
spired research from both the electrical interconnect (EI) [7], [18]-[20]
and optical interconnect (OI) [21],
[22] perspectives.
The EI has coexisted with process
developments from the beginning and
is very mature and reliable in today's
semiconductor technologies. It dominates on-chip communication through
metallic transmission lines. However,
the highest achievable data rate across
distances of >10 mm is constrained
by the limited metal trace bandwidth,
with the loss increasing quadratically
with the signal bandwidth. To mitigate the narrowband issue, Chang's
group at the University of California, Los Angeles, has investigated
radio-frequency (RF) interconnects
through different frequency division
schemes [8]-[10]. At a distance measured approximately in meters, the EI
faces significantly lower supportable
data rates and less energy efficiency.
The OI aims to leverage ultralow-loss
and ultrawide-bandwidth optical
fibers to boost energy efficiency and
bandwidth density, thus dominating
long-distance wired communication.

(b)

The interconnect also inspires
active OI research fields, such as in--
tegrated photonics and silicon pho-
tonics [3], [21], [22]. However, indirect
bandgap silicon material presents a
fundamental challenge for high-efficiency on-chip optical sources. The
multichip module (MCM) solution is
the current mainstream approach for
small form factors [21], [22]. However,
the die-to-die bandwidth density is
still constrained by the system-onchip serializer/deserializer (SerDes)
capabilities. To remove the SerDes
constraint and its power consumption, more adv a nced pack ag ing
approaches have been investigated,
such as the embedded multidie interconnect bridge [11] and interposers.
However, these complex integration
approaches come with a high cost
due to low yields and a poor screen
for the known good die [12]. Other
issues, such as temperature and environment sensitivity and stringent
alignment requirements, necessitate
more sophisticated and dedicated
manufacturing, which also results in
significant expenses. Therefore, for
an interconnect at a distance measured roughly in meters, the OI also
faces the challenges of high costs,
significant power consumption, and
degraded energy efficiency. In summary, short-reach, off-chip communication up to a few meters is the
biggest challenge, where both the EI
and the OI encounter fundamental
difficulties. Furthermore, as shown

(c)

FIGURE 1: (a) Different types of data traffic growth rate through the years [4]. (b) The I/O bandwidth requirement and pin number evolution
through time [5], [6]. (c) The interconnect FOM versus the communication distance for different technologies [13]. SerDes: serializer/deserializer;
PCIe: peripheral component interconnect express; ISSCC: International Solid-State Circuits Conference; GbE: gigabit ethernet; CPRI: common
public radio interface; SR: short range; LR: long range; LVDS: low-voltage differential signaling; PMA: physical media attachment; PCS: physical
coding sublayer; BOA/MBOM: board-mount optical assembly/mid-board optical modules; SR4: short-range, four-channel; GBASE: gGbit baseband signaling.

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IEEE Solid-States Circuits Magazine - Fall 2020

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