IEEE Solid-States Circuits Magazine - Fall 2020 - 54

The Open Source Revolution
The hardware community is current-
-ly experiencing an open source revo-
lution, from the proliferation of the
RISC-V architecture to the generation
of the open source intellectual prop-
erty (IP) used in the design process,
such as the NVIDIA Deep Learning

C++ Design
C++ Design
Libraries

Architecture (NDVLA), to improve
reusability. Open source HDL code,
including OpenCores [15], has been
around for decades, yet open source
toolchains for chip design have only
recently ga ined popula r it y. The
reason for this is that open source RTL
gets the designer only so far, as the

C++ Simulation

C++
Test Bench

Coverage
Collection
Verified C++
Model

HLS
Constraints

HLS
Compilation
HLS-Generated
RTL

RTL Simulation
Key
Designer Inputs
Intermediate Files
Tools

RTL Coverage
Collection
Verified RTL
Model
Standard ASIC
Back-End Flow

7
6.5
6
5.5
5
4.5
4
3.5
3

12
10
Speedup

Speedup

FIGURE 6: The object-oriented HLS design methodology used for designing the inference
accelerator chip.

ecosystem of modern chip design
tools is vast and often proprietary.
Recent efforts, such as the OpenRoad
Project [16], have tried to address this
problem, enabling engineers to take
their designs all the way to the GDS
using a fully open source toolchain.
In the software community, the
idea behind the open source move-
ment's success is that building
on top of preexisting, preverified
work leads to increased productiv-
ity and quality for all. There have
been open source operating systems
and compilers for decades, but the
hardware community is still catch-
ing up. Our inference accelerator
chip design at NVIDIA involved the
integration of RISC-V IP and library
components from an open source
library for HLS design. In MatchLib,
highly parameterized models were
designed and reused to exploit their
flexibility. Combining these highlevel hardware models in the Match-
Lib library with HLS enabled further
flexibility and design space explo-
ration opportunities, as each piece
of source code was not limited to a
particular microarchitecture or lowlevel implementation.
We are also beginning to see indus-
try support for open source ASIC
design, including the recent announce-
ment by Google and the Free and Open
Source Silicon (FOSSi) Foundation that
they will provide an open source PDK
to produce chips in a 130-nm technol-
ogy node [13]. Within this initiative,

8
6
4

0

500 1,000 1,500 2,000 2,500 3,000 3,500 4,000
Directed Test ID
(a)

2

0

500 1,000 1,500 2,000 2,500 3,000 3,500 4,000
Directed Test ID
(b)

FIGURE 7: The simulation speedup gains from simulating the RTL with a commercial simulator versus a standard C++ toolchain for designs
from the inference accelerator. (a) The C++/RTL speedup for the PE. (b) The C++/RTL speedup for the GB.

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