IEEE Solid-States Circuits Magazine - Fall 2020 - 55

manufacturing is free so long as
designs are open source all the way
down to the GDS. This helps democ-
ratize chip design such that everyone
who is interested can access tools
and foundry resources to design and
produce their own silicon. Increas-
ing accessibility to tools and flows
provides students and hobbyists
with further access to the experience
needed to make an impact in our field.
By democratizing the code, tools, and
process to obtain silicon, we increase
the levels of exposure to the IC design
process. This provides an opportunity
to create the perception of continuous
innovation to recruit the next genera-
tion of talent.

Next Steps
The past decade saw productivity gains
from mature EDA tool development and
the integration of improved processes
to keep pace with growing compute
demand. The next era of productivity
in chip design is trending toward the
use of big data and machine learning
to accelerate design automation. No
longer just an application target for
hardware acceleration, machine learn-
ing has the potential to source addi-
tional productivity gains from digital,
analog, and system design that have
traditionally been left on the table. Lots
of useful data are generated during the
chip design process, including simu-
lation results from regressions, code
check-ins, and runtime information
from a back-end EDA flow. These data
can be used in new and exciting ways,
such as improving floorplanning tech-
niques prior to place-and-route [17]
and even accurately predicting parasit-
ics in analog layouts [18]. As with any
machine learning approach, designing
something radically different than the
training set can lead to nonsensical
results, so designers still need circuit
design expertise for sanity checking.
This process involves expertise from
data science, GPU-accelerated com-
puting, and open source (software)
tools, such as PyTorch and TensorFlow,
to train and deploy neural networks
using just a handful of commands due
to the benefits of library-based design

and reuse prevalent within the soft-
ware community.
Ever-increasing complexity is one
of the few certainties in electronic
design, and the cycle of progress
continues: having more transistors per
chip enables more compute power,
which facilitates the design of more
complex software, improving the capa-
bilities of chip design tools and eventu-
ally enabling designers to build more
complex chips. Software design skills,
frameworks, and methodologies are
becoming more foundational, leading
to merged skill sets across peripheral
disciplines, such as EDA and archi-
tecture. This merging process has
the potential to close the semantic
gap between software and hardware,
leading to new opportunities for talent
to enter the field via increased acces-
sibility. What it means to " think at
the transistor level " will continue to
evolve for digital designers, who have
the increasing automation of low-level
design decisions to get the most from
the " VLS " in VLSI.

Acknowledgment
The work referenced in this article
would not be possible if not for the
combined efforts of my colleagues
at NVIDIA Research.

References

[1] N. Singer, " The hard part of computer
science? Getting into class, " NY Times,
Jan. 24, 2019. [Online]. Available: https://
www.nytimes.com/2019/01/24/technolo
gy/computer-science-courses-college.html
[2] P. Thibodeau, " A tech bubble killed com-
puter science once, can it do so again? " IEEE
USA InSight, July 19, 2017. [Online]. Avail-
able: https://insight.ieeeusa.org/articles/
a-tech-bubble-killed-computer-science
-once-can-it-do-so-again/
[3] " How to be an employer of choice for Gen
Z, " Workforce Institute @ Kronos, 2019. [On-
line]. Available: https://workforceinstitute
.org/wp-content/uploads/2019/11/How-to
-Be-an-Employer-of-Choice-for-Gen-Z.pdf
[4] B. Zimmer et al., " A 0.32-128 TOPS, scal-
able multi-chip-module-based deep neural
network inference accelerator with groundreferenced signaling in 16 nm, " IEEE J. SolidState Circuits, vol. 55, no. 4, pp. 920-932, Apr.
2020. doi: 10.1109/JSSC.2019.2960488.
[5] " MatchLib, " GitHub, NVIDIA. [Online]. Avail-
able: https://github.com/NVlabs/matchlib
[6] B. Khailany et al., " A modular digital VLSI
flow for high-productivity SoC design, " in
Proc. 55th Annu. Design A
- utom. Conf. (DAC
'18), 2018, pp. 1-6. doi: 10.1145/3195970.
3199846.
[7] M. Fojtik et al., " A fine-grained GALS SoC
with pausible adaptive clocking in 16 nm
FinFET, " in Proc. 25th IEEE Int. Symp. Asyn-

chronous Circuits Syst. (ASYNC), Hirosaki, Ja-
pan, 2019, pp. 27-35. doi: 10.1109/ASYNC.
2019.00012.
[8] A. Feldman, " a massive wafer-scale super-
computer for deep learning -acceleration:
A radically new paradigm for deep -learning
acceleration, " presented at the 57th DAC,
San Francisco, CA, June 20-24, 2020.
[9] B. Bailey, " Hidden costs of shifting left, "
Semiconductor Engineering, Apr. 26, 2018.
[Online]. Available: https://semiengineering
.com/hidden-costs-of-shifting-left/
[10] S. Jiang, B. Ilbeyi and C. Batten, " Mamba:
Closing the performance gap in produc-
tive hardware development frameworks, "
in Proc. 55th ACM/ESDA/IEEE Design Autom. Conf. (DAC), San Francisco, 2018, pp.
1-6. doi: 10.1109/DAC.2018.8465576.
[11] J. Bachrach et al. " Chisel: Constructing
Hardware in a scala embedded language, "
in Proc. Design Autom. Conf. (DAC), June
2012. doi: 10.1145/2228360.2228584.
[12] L. P. Carloni, " From latency-insensitive
design to communication-based systemlevel design, " Proc. IEEE, vol. 103, no. 11,
pp. 2133-2151, Nov. 2015. doi: 10.1109/
JPROC.2015.2480849.
[13] I. Cutress, " Hot chips 31 live blogs: Tesla
solution for full self-driving, " AnandTech,
Aug. 20, 2019. [Online]. Available: https://
www.anandtech.com/show/14766/hotchips-31-live-blogs-tesla-solution-forfull-self-driving
[14] P. Wagner, " Produce your own physical
chips. For free. In the open, " FOSSI Foun-
dation, Halifax, U.K. [Online]. Available:
https://fossi-foundation.org/2020/06/30/
skywater-pdk
[15] OpenCores. Accessed: Aug. 15, 2020. [On-
line]. Available: https://opencores.org/
[16] The OpenROAD Project. Accessed: Aug. 15,
2020. [Online]. Available: https://theopen
roadproject.org/
[17] Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany,
and D. Z. Pan, " DREAMPlace: Deep learn-
ing toolkit-enabled GPU acceleration for
modern VLSI placement, " in Proc. DAC,
2019, pp. 1-6.
[18] H. Ren, W. Turner, G. Kakai, and T. Ku,
" ParaGraph: Layout parasitics and device
parameter prediction using graph neural
networks, " in Proc. DAC, 2020, pp. 1-6.

About the Author
Alicia Klinefelter (aklinefelter@nvidia
.com) received her Ph.D. degree in elec-
trical engineering from the University
of Virginia, Charlottesville, in 2015. She
joined NVIDIA in January 2017 and is
currently a senior research scientist in
the ASIC and very large-scale integra-
tion (VLSI) research group. Her Ph.D.
thesis explored VLSI architectures for
digital signal processing on energyconstrained systems on chip and was
completed under the guidance of Prof.
Ben Calhoun. Her research interests
include low-power circuit design, arith-
metic and elementary function circuits,
design effort reduction techniques, and
emerging verification approaches for
high-level languages.

IEEE SOLID-STATE CIRCUITS MAGAZINE

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https://semiengineering.com/hidden-costs-of-shifting-left/ https://semiengineering.com/hidden-costs-of-shifting-left/ https://www.anandtech.com/show/14766/hot-chips-31-live-blogs-tesla-solution-forfull-self-driving https://www.anandtech.com/show/14766/hot-chips-31-live-blogs-tesla-solution-forfull-self-driving https://www.anandtech.com/show/14766/hot-chips-31-live-blogs-tesla-solution-forfull-self-driving https://www.anandtech.com/show/14766/hot-chips-31-live-blogs-tesla-solution-forfull-self-driving https://fossi-foundation.org/2020/06/30/skywater-pdk https://fossi-foundation.org/2020/06/30/skywater-pdk https://www.opencores.org/ https://theopenroadproject.org/ https://theopenroadproject.org/ https://www.nytimes.com/2019/01/24/technology/computer-science-courses-college.html https://www.nytimes.com/2019/01/24/technology/computer-science-courses-college.html https://www.nytimes.com/2019/01/24/technology/computer-science-courses-college.html https://insight.ieeeusa.org/articles/a-tech-bubble-killed-computer-science-once-can-it-do-so-again/ https://insight.ieeeusa.org/articles/a-tech-bubble-killed-computer-science-once-can-it-do-so-again/ https://insight.ieeeusa.org/articles/a-tech-bubble-killed-computer-science-once-can-it-do-so-again/ https://workforceinstitute.org/wp-content/uploads/2019/11/How-to-Be-an-Employer-of-Choice-for-Gen-Z.pdf https://workforceinstitute.org/wp-content/uploads/2019/11/How-to-Be-an-Employer-of-Choice-for-Gen-Z.pdf https://workforceinstitute.org/wp-content/uploads/2019/11/How-to-Be-an-Employer-of-Choice-for-Gen-Z.pdf https://www.github.com/NVlabs/matchlib

IEEE Solid-States Circuits Magazine - Fall 2020

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