IEEE Solid-States Circuits Magazine - Fall 2020 - 58

from losing charge with time. In the
3D NAND cell, a thin layer of chargetrapping material is used to retain
charge. This layer of charge-trapping
material is also continuous between
word lines for ease of processing. The
charge can move from one cell to the
next cell or be stuck in between cells
(i.e., word lines). Fortunately, the
charge movement is only between
the word line layers in 3D NAND, and
there are sufficient electrons per cell
to endure potential losses of trapped
charges, which reduces data loss dur-
ing data retention. Intel/Micron used
floating gates in its 3D NAND archi-
tecture and claim to have better data
retention in its QLC product [9].
For efficient packing, NAND archi-
tecture has been mostly two planes
with long word lines and long bit
lines. As an example, the most re-
-
cent chip, 96-L BiCS4 QLC 1.33 Tb
[11], has a word line up to 6 mm in
length and bit lines as long as 10 mm.
Due to the nature of slow NAND
flash tunneling and the low cur-
rent needed to program each cell,
large numbers of cells can be pro-
grammed at the same time, which
boosts the write throughput. The
conventional way is to sense half of
the bit lines at a time to shield the
bitline-to-bitline capacitive coupling

[12]. A lot of NAND manufactures
used this conventional half-bit-line
architecture for many years. SanD-
isk (before becoming Western Digi-
tal) invented an all-bit-line (ABL)
sensing and programming scheme
to double the write throughput [13].
Now all NAND architectures use ABL
architecture to achieve a higher read
and write throughput [1]. Each bit
line is connected to a set of sense
amplifiers (SAs): a typical architec-
ture is shown in Figure 2(c), where
the SA/peripheral is located at the
side of the chip. The input-output
(I/O) and power pads on the NAND
are located at one side of the chip to
enable multidie packaging. In 3D
NAND memory, as shown in Figure 2(a),
the SA and peripheral circuits are
like a ranch house in a crowded met-
ropolitan downtown, where land is
very precious. As the memory build-
ings grow taller, the peripheral cir-
cuits take a higher percentage of
the total die size. As a result, 3D
NAND scaling cost benefits are re--
duced accordingly.
To overcome the issue of periph-
erals taking up too large an area and
too high a percentage of the total die
size, a few different architectures
were explored. As shown in Figure 2(b),
the peripheral circuit can be hidden

underneath the array [CMOS under
array (CUA)], like building an under-
ground garage in the city [14]. Another
alternative is to build the peripheral
circuits on a different CMOS wafer
and then bond the memory wafer
with the CMOS wafer using wafer-towafer microbonding, termed CMOS
bonded array (CBA) [15]. The two
architectures are similar in the sense
that the peripheral circuits overlap
with the memory array areas. The
difference is that CBA builds the CMOS
on a totally different wafer. The CUA
advantage is that the memory and
CMOS are built on the same wafer,
reducing wafer cost. The disadvan-
tage is that the thermal processes
needed to anneal the memory array
also impact the CMOS transistors on
the same wafer, which can degrade
the CMOS transistor's -
c apability.
The CBA has the advantage of CMOS
being processed on a different wafer
from the memory array to avoid the
extra thermal impact, so the CMOS
quality is better able to produce
higher interface I/O speeds. The dis-
advantage of CBA is the cost of pro-
cessing two wafers, along with the
cost of extra mechanical bonding
processes between two wafers. Mil-
lions of micro bumps are bonded on
in this process.

3D Flash Memory
BiCS Flash

2D Flash Memory

Channel:
Poly-Si Tunnel Layer: SiON
Memory Layer: Si(O)N
Block:
SiO/High-k
Stack

Control Gate:
Metal
(a)

(b)

(c)

FIGURE 1: The 2D NAND string flat on silicon: (a) stand up and (b) multiply. (c) Three-dimensional cylindrical (macaroni) cells: a poly-silicon
(poly-Si) channel, tunneling layer [silicon oxynitride (SiON)], charge-trapping memory layer [Si(O)N], blocking layer, and control gate in metal
(word line).

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