IEEE Solid-States Circuits Magazine - Fall 2020 - 9

Most of our design effort is expended on selecting the transistor
dimensions in Figure 1. We generally
begin with near-minimum dimensions unless there is a compelling
reason not to do so. Also, our simulations are performed under worstcase process, supply voltage, and
temperature (PVT) conditions because
the circuit must eventually operate satisfactorily in such a corner. In
this spirit, we select the slow-slow
corner, VDD = 1 V - 5% = 0.95 V, and
T = 75c C. We also assume for the
clock a 50% duty cycle and 10-ps rise
and fall times. The comparator is designed using 28-nm CMOS technology.

Choice of Device Dimensions
Comparator design begins with selecting the transistor dimensions so
as to meet the offset requirement.
In our case, the pairs M1 and M2, M3
and M4, and M5 and M 6 in Figure 1 appear in the signal path and must be
crafted first. Let us consider M1 and
M2 and write their threshold voltage
mismatch as

DVTH1,2 =

A VTH ,
(1)
(WL) 1, 2

where AVTH is a constant [5] and
roughly 2.2 mV µm in 28-nm technology. If we choose W 1, 2 = 10 nm
and an effective length of 25 nm,
then DVTH = 4.4 mV. This appears to
be a reasonable starting point provided that the other pairs' contributions do not raise the offset beyond
the 5-mV target.
We should remark that (1) gives
the standard deviation, v, of the
mismatch; i.e., approximately 68%
of the differential pairs in a Gaussian distribution exhibit offsets less
than this amount. In practice, we
seek higher yields and must either
enlarge the transistors or incorporate offset cancellation.
The tail transistor M7 in Figure 1
must draw sufficient current with
VGS7 = VDD and VDS7 = Vin, CM - VGS1,2,
where Vin, CM denotes the input
com mon -mo de (CM ) level. Wit h
Vin, CM = 0.5 V and VGS1, 2 . 0.35 V, we
have VDS7 . 0.15 V. The device thus
operates in the deep triode region.

a width of 0.5-1 μm can meet this
constraint.

Let us select W 7 = 2 nm for a current
of roughly 0.5 mA.
Given that the circuit provides gain
before M3 and M4 turn on, we expect
that the offset of this pair is reduced
when referred to the main input. The
reduction factor is, in fact, greater
than the value of 2g m1, 2 VTH3,4 /I SS
mentioned previously. To understand why, suppose M3 and M4 are on
(Figure 3) and neglect the capacitances at nodes P and Q. Thus, I D1 and
I D2 entirely flow through M3 and M4,
respectively, as if these transistors
were absent. The offset contributed
by this pair is therefore negligible
unless the circuit's capacitances are
taken into account. As discussed later in this section, the threshold mismatch between M3 and M4 is divided
by a factor of 3-5 in typical designs.
We select W 3, 4 = 10 nm for now, expecting that this choice only slightly
raises the input offset.
The PMOS cross-coupled pair in
Figure 1 turns on after VX and V Y
fall by one 1-PMOS threshold. Before
this time, the circuit provides a high
voltage gain, thereby reducing this
pair's offset contribution considerably. In this respect, we surmise
that a width of a few microns suffices for M5 and M 6, but we must
bear in mind that these devices also
amplify regeneratively and play a
role in the comparator's speed. We
return to this point when we optimize the design.
The reset switches S1-S 4 in Figure 1 must pull their drain nodes to
VDD in under 100 ps. We predict that

Basic Waveforms
Based on our foregoing thoughts, we
construct the comparator shown in
Figure 4 and simulate it in the time
domain. The output inverters act as
buffers and employ relatively small
transistors for now. Before optimizing the design, we familiarize ourselves with the circuit's waveforms.

VDD

∆V

VP
VQ

TCK

Comparison Precharge
FIGURE 2: An example of dynamic offset.

ID1 IX

ID2

Q
M1

Vin1
CK

Vin2

FIGURE 3: The effect of the mismatch
between M3 and M4 in the absence of capacitances at P and Q.

VDD
CK
S1

M6
Vout

Q
M1

P
Vin1

WP = 400 nm

Vin2

WN = 200 nm
S1-S4: W = 0.5 µm
WP = 400 nm
W5,6 = 2.5 µm
W3,4 = 10 µm
Y
W1,2 = 10 µm
WN = 200 nm
W7 = 2 µm
L = 28 nm

FIGURE 4: The initial design of the comparator core.

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IEEE Solid-States Circuits Magazine - Fall 2020

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