IEEE Solid-States Circuits Magazine - Fall 2021 - 125

In addition to the educational experience,
it achieves several other objectives:
to demonstrate sparsity optimization
for lightweight machine learning
applications, contribute a complete
open source RISC-V-based SoC to the
community, and provide a framework
for future research.
The AFTx06 implements an RV32IM
instruction set, integer multiplication
and division, an integrated core local
interrupt (CLINT) controller and a platform-level
interrupt controller (PLIC),
and it is expected to operate with a
100-MHz clock. A key feature of this
microprocessor is the sparsity-aware
core extensions (SparCE) architecture
[2], a component that exploits sparsity
in convolution arithmetic, allowing
extraneous instructions (such as multiplication
by zero; common in rectified
linear unit functions) to be skipped at
run time. The architecture has been
designed to improve both the speed
and power consumption of this common
machine learning calculation.
The design architecture of the
SparCE module is shown in Figure 4.
The blocks within the dotted boundary
illustrate the interaction between
functional blocks. Signals outside the
boundary are inputs from and outputs
to the rest of the pipeline. The
Sparsity Register File (SpRF) is used
to dynamically track which registers
in the processor's register file contain
zero values. The SpRF contains one
entry corresponding to each register
in the register file. The SparCE Value
Checker (SVC) checks if the value
is zero and updates the SpRF correspondingly
when an instruction writes
to a register. The sparsity-aware skip
address (SASA) table is a cache-like
block with an associative memory
structure that stores the information
required to skip a region. Each entry
contains the program counter (PC)
state for the instruction prior to the
skippable region, a field that stores
the condition for the region to be skippable,
and the number of instructions
that can be skipped.
The preidentify and skip redun -
dancy unit (PSRU) uses the SASA
table to identify and skip redundant
code blocks. For each instruction, it
checks if the PC matches an entry in
the SASA table. An entry in the SASA
table indicates that the instruction
following the current instruction is
the start of a potentially skippable
region. In this case, the PSRU checks
the SpRF to identify if the registers
indicated in the SASA table entry
are currently zero. If so, it advances
the PC to the end of the redundant
instruction sequence. The control
flow instruction detector (CFID)
decodes the instruction in the de -
code stage rather than waiting for
the instruction to be decoded in the
execute stage. This allows control
Self-Test
ROM
6 × 2 kB
SRAM
Memory
Controller
AHB
Lite
Interface
PWM
AHB-APB
Bridge
Timer I2C
SPI GPIO
AHB Lite Master Multiplexer
CLINT
Controller
UART
Debugger
Wishbone
Interface
APB: Advanced Peripheral Bus
I2C: Interintegrated Circuit
SPI: Serial Peripheral Interface
FIGURE 3: A block diagram of the AFTx06 architecture. SRAM: static random-access memory;
AHB: Advanced High-Performance Bus; PWM: pulsewidth modulation; GPIO: general-purpose
input/output; UART: universal asynchronous receiver-transmitter; CLINT: core local interrupt; PLIC:
platform-level interrupt controller; RV32IM: RISC-V 32-bit integer instruction set with M-extension.
RISC-V Core
RV32IM
With Sparsity
Optimization
External
PLIC
wb_data
SVC
is_sparse
wb_en
SpRF
sasa_rs1 sasa_rs2
pc
sasa_addr
sasa_wen
sasa_enable
sasa_data
SASA Table
insts_to_skip
preceding_pc
condition
valid
pc
PSRU
sasa_addr
rs1_sparsity
rs2_sparsity
wb_data
ctrl_flow_enable
CFID
FIGURE 4: The sparsity implementation. SpRF: sparsity register file: SVC: SparCE value checker;
SASA: sparsity-aware skip address; PSRU: preidentify and skip redundancy unit; CFID: control
flow instruction detector.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
125

IEEE Solid-States Circuits Magazine - Fall 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021