IEEE Solid-States Circuits Magazine - Fall 2021 - 126

flow instructions to have a higher
precedence than skipping. To exploit
the sparsity feature, an LLVM-based
compiler was modified to identify
skippable code regions and generate
data to populate the SASA table
during bootup of the process.
The authors wish to acknowledge
the SSCS for the sponsorship of
our tape-out; Efabless, Google, and
SkyWater Technology for enabling
the PDK infrastructure; the Scalable
Asymmetric Lifecycle Engagement
Microelectronics Workforce
Development program sponsored by
the U.S. Office of the Secretary of
Defense; and the many students who
have generated hardware IP, verification
IP, software infrastructure, and
design flow scripts.
-J. Martinuk and M.C. Johnson
Elmore Family School of Electrical
and Computer Engineering,
Purdue University
Voltage-Controlled OscillatorBased
Analog-to-Digital
Converter for Internet of
Things Applications
Contributing to the open source
movement, we designed a voltagecontrolled
oscillator (VCO)-based
analog-to-digital converter (ADC)-
a mixed-signal design for Internet
of Things (IoT) applications-and
implemented this design using the
SkyWater 130-nm open source PDK
and purely open source EDA tools
and IPs.
Many IoT applications need to collect
data from the environment using
sensors; therefore, a low-cost and lowpower
integrated ADC is essential for
IoT SoCs. A VCO-based ADC architecture
has a small hardware area and
a low power consumption, making it
suitable for IoT applications. In addition,
most parts of the design are
digital and can be easily reused and
ported to new technologies.
Our ADC uses a sigma-delta (ΣΔ)
architecture with first-order noise
shaping, as shown in Figure 5. First,
the VCO encodes the voltage level
of the input signal into the speed
of pulses. After that, a multiphase
readout implements ΣΔ modulators
126
FALL 2021
to sample the pulses in each clock.
Finally, a third-order cascaded integrator
comb (CIC) filter is applied to
reduce the sampling rate of the ADC
and improve the signal-to-noise
ratio. Our targeted input signal
bandwidth is 100 kHz, which is suitable
for low-speed sensor readouts
and audio applications. The oversampling
rate and the oversampling
clock are configurable up to 1,024
and 50 MHz, respectively.
The main challenge in this work
is to design the VCO with high linearity,
which affects the overall
ADC performance. The VCO is fully
customized with 11 cross-coupling
inverters specially tuned for high
linearity from 2 to 10 MHz. It has
been simulated using an open source
simulator (Ngspice) and laid out
in Magic. Additionally, the digital
parts,
Future work will improve the ADC
performance and consider more
complex architectures.
We would like to give a special
thanks to the SSCS for sponsoring us
to tape out this project.
-D.-H. Bui, D.-M. Tran, N.-D.
Nguyen, M.-H. Dao, and X.-T. Tran
Information Technology Institute,
Vietnam National University,
Hanoi, Vietnam
including the phase
readout and CIC filter along with a
Wishbone bus interface to read out
the captured data in the two SRAMs,
are implemented using Openlane
[a register transfer level (RTL)-toGraphic
Design System (GDS) flow].
The VCO occupies a small area of
3,520 µm2
, while the digital part
takes up 73,000 µm2. The postlayout
simulation shows that our VCObased
ADC can achieve 10 effective
numbers of bits with an input voltage
Vpp = 0.8 V and a signal-to-noise
and distortion ratio of 58.6 dB with a
supply voltage Vdd = 1.8 V.
This work reused many IPs from
the open source hardware design
ecosystem on SkyWater 130 nm for
tape-out to shorten the design time.
For example, the pad rings, the
management SoC, and the phaselocked
loop (PLL) are reused from the
Caravel Test Harness, while the static
random-access memory (SRAM)
macros are from the OpenRAM
project. Thanks to the open source
ecosystem, we can complete this
project from concept to layout in two
months without knowing these EDA
tools in advance. Figure 6 presents
the final layout of the Caravel User
Project Wrapper, which contains
three VCO-based ADCs with different
configurations for testing.
IEEE SOLID-STATE CIRCUITS MAGAZINE
Sermo-soc
Sermo-soc is a motor controller subsystem
that serves as a research vehicle
for the design-space exploration
of novel motor-control algorithms. It
turns the Efabless Caravel SoC into a
powerful servomotor controller that
provides four programmable proportional-integral-derivative
(PID) control
units with quadrature encoder
inputs (QEIs) and pulsewidth modulation
(PWM) outputs. In addition,
eight delta-sigma inputs (DSIs) with a
fully programmable and dynamically
reconfigurable digital filter datapath
are provided for current, voltage,
and condition monitoring. Finally,
two coordinate rotation digital computer
(CORDIC) (sine) instances are
provided to accelerate trigonometric
calculations in advanced vector control
algorithms. With these peripherals
and accelerators, sermo-soc
can be employed in the high-performance
sensored and sensorless
control of dc/ac motors, with applications
ranging from home appliances
to quadcopters to the power trains of
electric vehicles. The peripherals are
connected to Caravel general-purpose
input/outputs (GPIOs), whereas
all of the configuration registers are
memory-mapped on the Caravel's
Wishbone slave interface, except the
CORDIC instances, which are connected
to Caravel's logic analyzer
(LA) interface. The SoC block diagram
is shown in Figure 7 with use cases
of dc servocontrol as well as vector
control of ac motors.
Programmable PID Control Unit
The PID controller implements the
conventional, closed-loop feedback
control of dc servomotors. A PWM
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