Package and On-Chip Wiring Inductance VDD Damping Resistor Active Circuitry VSS (a) (b) On-Chip Bypass Cap Active Circuitry Active Circuitry Active Circuitry (c) (d) Active Circuitry Active Circuitry C0 C1 C2 R1 R2 (e) (f) FIGURE 5: Options for on-chip supply de-Qing: (a) The simplified undamped network. (b) Seriously? (c) Self defeating. (d) Career limiting. (e) Practical solution. (f) Square-root-of-s improvement. S-1/2 Log Frequency (a) Log Frequency (b) FIGURE 6: Straight-line Bode approximations for conventional damping (dashed lines) and square-root-of-s damping (solid lines). (a) Efficient use of capacitance for a given inductor range. (b) Extension of safe zone for a given capacitor efficiency. 18 FALL 2021 IEEE SOLID-STATE CIRCUITS MAGAZINE Log Impedance Power Supply (ac Short) DC-Blocking Capacitor Log Impedance Damping Resistor Damping Resistor Damping Resistor Square-Root-of-s Range of Safe Inductance Bypass Capacitance Total Capacitance Figure 5(e) Range of Safe Inductance Two-Capacitor Solution: Figure 5(e) Square-Root-of-s Solution Total Capacitance Range of Safe Inductance S-1/2