IEEE Solid-States Circuits Magazine - Fall 2021 - 36

sleep mode for 4 s before attempting
to sample again. If the voltage is above
3 V, the system transmits a packet and
then returns to periodically sampling
the voltage to determine when to
transmit the next packet [31].
MoS2 for Flexible Electronics
The growing interest in foldable and
lightweight electronic systems has
helped the development of different
flexible semiconductor technologies,
which have the potential to replace
rigid silicon. Flexible materials can
significantly improve the design of
implantable and wearable devices as
well as a new generation of prosthetic
limbs and robots. Flexible electronics
can also enable smart textiles with embedded
sensors for monitoring various
vital signals of the human body.
Despite the great interest in developing
transistors on flexible substrates,
most of the approaches pursued thus
far have very limited performance in
terms of mobility and yield, or their
fabrication process is very complex.
For example, organic semiconductors
have typical carrier mobilities below
1 cm2/(V s), and amorphous metal
oxides show a performance shift under
illumination or thermal stress.
Carbon nanotube-based electronics
show improved performance, however,
they still suffer from metallic-impure
tubes, which result in complex
and additional fabrication-processing
steps [32].
On the other hand, few-layer-thick
MoS2 has the potential to overcome
many of these challenges. Strong intralayer-covalent
bonds confer MoS2
crystals excellent mechanical strength,
thermal stability, and a surface free of
dangling bonds. At the same time, single
layers of MoS2 can be grown over large
areas using chemical vapor deposition
(CVD), and their wide bandgap (WBG)
(1.8 eV), high carrier mobility [120 cm2/
(V s) at room temperature, 34,000 cm2/
(V s) for 6-L exfoliated MoS2 at low temperature,
and 1,020 cm2/(V s) for 1-L
CVD monolayer at low temperature],
planar nature, and mechanical flexibility
make them excellent candidates for
the fabrication of transistors for both
36
FALL 2021
analog and digital circuits. Despite the
promising characteristics of MoS2, applications
thus far have been limited
to single or a few devices due to the
many challenges associated with the
uniformity and yield control in both
material growth and device technology
as well as a lack of an enhancementmode
(E-mode) transistor technology.
This work pushes the MoS2 technology
forward by demonstrating E-mode
transistors, compact modeling, and a
custom CAD flow to enable complex circuits
for the first time, as demonstrated
in Figure 14.
The proposed design flow includes
a gate-first process where all the
passive components are fabricated
before the MoS2 transfer. This approach
minimizes the fixed charge
in the gate dielectric of MoS2 transistors,
as shown in Figure 15. This results
in MoS2 transistors with small
subthreshold voltage swing and
positive threshold voltage and tight
statistical distribution, which are essential
for the successful design of
multistage-cascaded circuits. Second,
compact, virtual-source device models
are used to capture the different
regions of device performance (subthreshold,
linear, and saturation) and
predict future field-effect transistor
(FET) performance as the fabrication
process evolves.
Third, a CAD flow is developed for
the design, simulation, and layout of
MoS2-based circuits using an industrystandard
IC design environment. A
variety of combinational (inverter,
NAND, NOR, AND, OR, XOR, XNOR) and
sequential logic circuits (latch, edgetriggered
registers) as well as switchedcapacitor
dc-dc converters have been
designed, fabricated, and characterized,
showing the correct functionality, as depicted
in Figure 16. Figure 17 illustrates
the schematic, micrograph, and measurement
results of the fabricated
switched-capacitor dc-dc converter.
With the demonstrated fabrication
technology, modeling, and CAD flow,
this article provides a platform for the
co-optimization of circuits and devices
using MoS2, while the fabricated circuits
show the great promise of the
IEEE SOLID-STATE CIRCUITS MAGAZINE
technology for realizing complex systems
[11], [32], [33].
Neural Networks for
Energy-Efficient Computing
With rising expectations for the broad
deployment of secure image, audio,
and handwritten text recognition on
energy-constrained devices, traditional
digital computing is not efficient
enough to accomplish these tasks,
even with brain-inspired computing
architectures like neural networks.
Analog computing returns due to its
low-power consumption nature and
convenience of near-sensor computation
[34]. However, increasing the
precision of analog computing leads
to higher energy consumption because
robust analog circuit design is
challenging due to transistor imperfections
and reduced supply voltage
while designing with advanced
technology nodes. Luckily, research
shows that the weight precision in
neural networks can be reduced [35].
This allows analog computing to be
used in machine learning hardware.
The multiply-and-accumulate operation
is widely used in scientific computing.
Analog computing can be operated
in both the charge and time domains.
The passive switched-capacitor
method in the charge domain has
the benefit of being highly amenable
with the nanometer CMOS process. In
contrast, time-domain approaches are
vulnerable to variations in process,
voltage, and temperature. A passive
switched-capacitor matrix multiplier
was proposed in [34]; however, its
weight and output resolutions were
fixed at 3 and 6 b, respectively, which
prevent the cell from being applied to
more applications. A reconfigurable
switched-capacitor-based MACUs was
proposed to achieve high-efficiency
computing in [34]. As shown in Figure
18(a) and (b), a digital-to-capacitance
converter is used to make the
weight resolution tunable between
2 and 6 b, and a reconfigurable synthetic
aperture radar analog-to-digital
converter (ADC) is applied to make
the output reconfigurable between 6
and 9 b.
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