IEEE Solid-States Circuits Magazine - Fall 2021 - 38

Both the time-domain wave and the
frequency-domain spectrum prove the
effectiveness of MACUs. The third
implementation is image filtering, as
depicted in Figure 19(d). A convolutional
filter is applied to an image to detect
the edges. The weight and output resolutions
are 6 and 9 b, respectively [36].
Au
Si/SiO2 Substrate
Ohmic Contacts
Cr/Au/Pd
Gate Deposition
Al2O3
ALD
Dielectric
Annealing
MoS2 Transfer
PMMA Removal
MoS2 Mesa Etch
MoS2
Conclusion and Future Directions
New technologies are emerging to
break existing limits and provide new
features for silicon chips. This article
presented six emerging technologies
that can enable innovative, miniaturized,
and energy-efficient electronics
for biomedical and power management
applications. The other promising
emerging technologies are also
listed in the following sections, classified
into three categories: 1) new materials
and devices, 2) new circuit- and
system-implementation techniques,
and (c) new silicon-based applications.
Ti/Au
Via Etch
Pads Deposition
FIGURE 15: The fabrication process of an inverter. The fabrication process of the transistors
starts with cleaning a separate target silicon dioxide (SiO2)/Si substrate using nanostrip (Cyantek
KMG) and hydrochloric acid. The transistor gate is then formed using a stack of 5-nm
chromium (Cr), 30-nm gold (Au), and 30-nm palladium (Pd). After that, gate patterning is
performed using photolithography. A 30-nm-thick aluminum oxide (Al2O3) layer deposited by
atomic layer deposition (ALD) is used as the gate dielectric. A via hole is patterned based on
the circuit layout, followed by reactive ion etching. The contact pads made of 5-nm titanium
(Ti)/90-nm Au-metal stacks are deposited before the MoS2 transfer. O2 plasma is then used
to isolate the MoS2. The ohmic contacts are formed by depositing 90-nm Au-layer transistor
channels [32]. PMMA: Poly(methyl methacrylate).
New Materials and Devices
Carbon nanotube FETs (CNFETs) are
a promising nanotechnology for
the development of energy-efficient
computing. Despite rapid progress,
CNFETs have only been fabricated in
academic or research laboratories.
A deposition technique in which the
substrate is submerged within a nanotube
solution can address these challenges
and can allow CNFETs to be
fabricated within industrial facilities
[38]. Graphene has been highlighted
as one of the most promising 2D materials
in the fields of electronics and
optoelectronics due to its great physical
properties. There are several methods
Voltage Divider
Diff-Comparator
INV
Ring
Oscillator
D-Flip Flop
XOR
XNOR
(Half-Added)
SR-Latch
(a)
(b)
FIGURE 16: (a) The cadence layout for large-scale circuits. The design flow is automatic and compatible with a large system design. (b) An
optical image of one of the chip dies. The different logic blocks are implemented here [32].
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