IEEE Solid-States Circuits Magazine - Fall 2021 - 47

frequency band is ~18 GHz from the
desired input frequency band, which
can be easily filtered by the frequency
selectivity of the antenna and the lownoise
amplifier prior to the RF mixer.
In Figure 3(b), LOs for the IF and
RF mixers are derived from the same
PLL, and their frequencies change together,
an arrangement called a sliding-IF
transceiver. In such a topology,
LO generation usually consists of a
fractional-N PLL and some frequency
multipliers and dividers to generate IF
LOs and RF LOs, as depicted in Figure 4.
The LO frequency can be reconfigured
by a different division ratio, N, and
multiplication factor, M, to support
multiple bands. It is also possible to
generate the two LOs independently
using two PLLs, which can potentially
relax the integrated PN (IPN) requirement
of each LO, as the PN of the two
independent PLLs is mostly uncorrelated,
whereas the desired signal is
correlated [13]. Nevertheless, the sliding
IF is still often in favor due to its
lower power consumption and smaller
chip area compared to employing two
PLLs [8], [10].
Figure 5 describes the top system
architecture of a 5G NR base station
system reported in [8]. In this example,
a 5-6-GHz fractional-N PLL is
multiplied by four and followed by an
in-phase/in-quadrature divide-by-two
to generate the IF LOs at ~10 GHz for
IF mixers. The same PLL output is fed
to a multiply-by-five circuit to obtain
RF LOs for RF mixers to support the
N260 frequency band (37-40 GHz).
To support N257 (26.5-29.5 GHz), the
multiplication factor can be changed
from five to three for RF LO generation.
Thus, the 5-6 GHz fractional-N
PLL can be reused to support 28- and
39-GHz bands. In such an LO generation
topology, the root mean square
(RMS) jitter of the total LO circuity
is ultimately determined by the
5-6-GHz fractional-N PLL, which is
similar to the case of LO generation
for sub-6 GHz. The additional noise
contribution from the frequency multiplier
circuitry can be minimized
through proper design techniques,
which will be explained later in detail.
As shown in Figure 5, phased-array
CMOS transceivers are usually employed
for FR2 to provide beamforming
and beam steering capabilities to
achieve the required high effective
isotropic radiated power in transmit
mode and low noise figure in receive
mode [8]-[15]. In addition to the circuit
blocks in Figure 3, phase shifters
are required in a phased-array transceiver,
which can be implemented in
the RF signal path, LO path, and digital
baseband. LO phase shifting is advantageous
in that the phase shifter loss
is not directly in the signal path, and
the nonlinearity and loss of active
phase shifters, such as phase interpolating
implementations [14], [15], are
more tolerable in the LO path than in
the signal path. However, since the undesired
interferences are rejected only
after the combining step at the IF, RF
amplifiers and mixers need to have a
higher dynamic range than those in
an RF phase shifting scheme. Moreover,
this requires multiple mixers
and complex LO distribution circuits,
which are power hungry. Alternatively,
the RF phase shifting scheme in Figure
5 is preferred, especially for handset
applications. By phase shifting
and signal combining at the RF before
the mixer, other radio blocks (i.e., the
mixer, LO generation, and baseband
circuitry) are shared among the paths,
resulting in reduced area and power
consumption. Thus, LO phase shifting
techniques are not discussed here.
To IF Mixers
0°
90°
Multiplier
and
Divider
I/Q Generation
(e.g., ÷ 2)
LO
Distribution
Buffers
×M1/N1
×M2/N2
Integrated Phase Jitter Requirement
for 5G LO Generation
The LO integrated jitter requirement
for FR2 bands is much more stringent
than it is for FR1 and 4G LTE applications.
A typical double sideband (DSB)
IPN of -30 dB relative to the carrier
(dBc) is needed to support 64-QAM and
2 × 2 MIMO under nonideal channel
conditions [13]. For a carrier frequency
of 28 GHz, this requirement translates
to a 171-fs RMS phase jitter (integrated
from 1 kHz to 100 MHz), which is similar
to the jitter requirement of 4G LTE
supporting 256-QAM and 4 × 4 MIMO
[16]. However, the required RMS jitter
becomes much tougher at higher carrier
frequencies, as shown in Table 1.
At the 47-GHz band, 107-fs RMS jitter
is needed for -30 dBc DSB IPN, which
is ~6 dB lower compared to the 28-GHz
band. Moreover, 256 QAM is likely to
be added in 3GPP release 17 to further
increase data rates, which may
require DSB IPN of -36 dBc [13] for
a good signal-to-noise ratio in MIMO
scenarios with channel fading. According
to Table 1, LOs of sub-100-fs
RMS jitter, and even as low as 50 fs,
may be required. This ultralow-jitter
performance is extremely challenging
to achieve for a fractional-N PLL implemented
in CMOS technology. To date,
only a handful of published PLLs have
demonstrated such low integrated jitter
performance, as plotted in Figure 6.
Figure 6 presents state-of-the-art
CMOS PLLs published in the literature
To RF Mixers
Fractional-N PLL
FIGURE 4: A generalized LO generation topology for sliding-IF transceivers.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
47

IEEE Solid-States Circuits Magazine - Fall 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021

Contents
IEEE Solid-States Circuits Magazine - Fall 2021 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2021 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2021 - Contents
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