IEEE Solid-States Circuits Magazine - Fall 2021 - 49

[6], [13], [16]-[37]. It includes both
integer-N and fractional-N PLLs operating
from a few gigahertz to
60 GHz. To compare the PLLs with
different output frequencies, the integrated
phase jitter, vt, is used, which
normalizes the IPN to the oscillator
frequency. Moreover, a power-
jitter figure of merit (FoM) defined
as
FoMt s
20 $
10
1
=+v^h loglog10
(Power/1 mW) is commonly used to
compare PLL performance [38], which
also takes power consumption into account.
In Figure 6, there is a clear performance
gap between PLLs operating
at mm-wave frequencies (>24 GHz) and
low RF frequencies (i.e., <15 GHz). The
few representative fractional-N PLLs
operating directly at mm-wave frequency
have an FoM of > -240 dB, with
an RMS jitter much higher than 100 fs.
It is not straightforward to point out
a single main reason for this performance
gap. The low quality factor of
the LC tank at mm-wave frequency
is clearly a limiting factor, which restricts
the oscillator PN and thus the
overall PLL RMS jitter.
Since the optimal PLL bandwidth
for minimum jitter is roughly where
the spectrum of the oscillator and
loop noise intersect, the oscillator
contributes ~50% of the PLL jitter in
an optimal case [38]. One method to
overcome this issue is to run the oscillator
at a lower frequency, where the
quality factor of the LC tank can be
maximized (e.g., ~10 GHz), and then
to frequency-multiply its output to
obtain the desired LO frequency [6],
as in Figure 5. The frequency multiplier
can be designed to have very low
noise [6], [39]-[41], resulting in a minor
increase of the overall RMS jitter.
Note that the multiplier consumes
additional power and may produce
undesired harmonics, which need
to be suppressed to meet spectrum
mask and coexistence requirements
in a cellular transceiver. Let us focus
on the low-jitter PLL design first.
Low-Jitter Fractional-N
PLL Architecture
Figure 6 includes PLLs of various architectures.
Three commonly used
fractional-N PLL topologies are depicted
in Figure 7. Figure 7(a) shows a
classic analog PLL, which consists of a
phase frequency detector (PFD) and a
charge pump (CP), an analog loop filter
(LF), a multimodulus divider (MMD),
and a voltage-controlled oscillator
(VCO). In contrast, a digital PLL (DPLL)
employs a time-to-digital converter
(TDC), followed by a digital LF (DLF)
to tune a digitally controlled oscillator
(DCO), as illustrated in Figure 7b. In
some DPLL implementations, the MMD
is replaced by a frequency counter for
simplicity, resulting in a first-order
delta-sigma modulation (DSM) [33],
[35]. However, a second- or third-order
DSM is usually required to provide
sufficient scrambling for near-integer
channels to prevent strong in-band
fractional spurs from significantly degrading
the PLL RMS jitter [42], [43]. A
digital-to-time converter (DTC)-based
sampling or subsampling PLL (SSPLL)
is presented in Figure 7(c), and it has
gained popularity in recent years.
TABLE 1. THE INTEGRATED PHASE JITTER REQUIREMENT
FOR 5G NR AT DIFFERENT BANDS.
DSB IPN REQUIREMENT
-30 dBc
-36 dBc
INTEGRATED PHASE JITTER AT CARRIER FREQUENCY
(INTEGRATED FROM 1 KHz TO 100 MHz)
29.5 GHz
64 QAM
256 QAM
171 fs
86 fs
40 GHz
126 fs
63 fs
43 GHz
117 fs
59 fs
47 GHz
107 fs
54 fs
PLL FoM = 20⋅log10 (σt/1 s) + 10⋅log10 (P/1 mW)
100
[32]
[33]
10-1
[34]
[28]
[16]
10-2
PLL With Tripler
[20]
[37] [31]
[23]
[22]
10-3
100
101
Power P (mW)
Fractional-N PLL
Integer-N PLL
PFD CP PLL
DTC-Based PLL Using SPD or SSPD
[ ] mm-Wave Frequency
[ ] RF Frequency
DPLL With TDC
Other Topologies
FIGURE 6: The jitter variance versus the power for state-of-the-art CMOS PLLs. FoM: figure
of merit; PFD: phase frequency detector; CP: charge pump; DTC: digital-to-time converter;
SPD: sampling PD; SSPD: subsampling PD; DPLL: digital PLL; TDC: time-to-digital converter.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
49
102
103
[24]
[36]
[26]
[25]
[27]
[30]
[29]
[13]
[6] Cascaded PLL
[21]
[19]
[18]
[35] PLL with
Tripler
[17]
>100 fs
<100 fs
PLL FoM = -230 dB
-240 dB
-250 dB
-260 dB
Jitter Variance σt2 (ps)2
IEEE Solid-States Circuits Magazine - Fall 2021

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