IEEE Solid-States Circuits Magazine - Fall 2021 - 51

as the digitally controlled finetuning
bank contributes additional
routing parasitics and QN [20], [30],
[33]. Therefore, an analog SPLL
could be preferred for low-jitter and
low-power wireless application despite
the tradeoff in analog LF size,
especially when a small loop bandwidth
is needed (e.g., 100 kHz).
This is not a big issue for 5G FR2
LO generation, as there is no stringent
spot noise requirement, and
only the total IPN matters. Thus, a
wide PLL loop bandwidth (typically
>500 kHz) is used to suppress the
VCO/DCO PN contribution for optimum
IPN.
Although SPLLs and SSPLLs are
promising for achieving lower jitter
due to a high KPD, their lockin
range is limited, especially for
SSPLLs, due to their dividerless operation
[21]-[31]. The lock-in range
of a PLL is defined as the maximum
frequency disturbance, fD, against
which a PLL can reacquire the target
frequency without a cycle slip
[46]. In general, the lock-in range
increases with the PLL sampling
frequency and loop bandwidth. To
extend the lock-in range, an auxiliary
frequency-locked loop (FLL) consisting
of a frequency divider and a
PFD with a predefined dead zone is
often employed in SSPLLs to assist
locking (for simplicity, this is not
shown in Figure 8) [26], [29], [31],
[44]. If the phase error at the input
of the PFD exceeds the dead zone
due to a large fD, the FLL kicks in
and corrects the fD.
Alternatively, [37] and [47] demonstrated
dividerless FLL implementations,
relying on increasing the PLL
sampling rate in FLL mode to enlarge
the lock-in range. Since the FLL is
concerned only with correcting an fD
event or assisting with the initial locking,
it can be implemented with very
low power (e.g., <1 mA). To strive for
low-jitter, high-performance operation
over process, voltage, and temperature
(PVT) variations, a hybrid
approach to leverage the advantages
of each PLL topology could be attractive.
This will be illustrated with a
DTC-based sampling analog PLL design
example.
Hardware Demonstration of a DTCBased
Sampling Analog PLL
Figure 9(a) is a system diagram of a
low-jitter DTC-based sampling analog
SSPD
CKREF
Vref
Vsmp
GM
+
-
CKVCO
CKVCO
CKREF
Vsmp = Vref
Phase Locked
Vref
Vsmp
CKREF Leads
(a)
CKDTC
CKREF DTC
SSPD
Vref
Vsmp
GM
+
-
CKVCO
KDTC
DTC Code
Φe (n)
(b)
CKDTC
CKREF
DTC
CKFB
MMD
KDTC
DTC Code
Φe (n)
(c)
or
CKDTC
CKREF
DTC
CKFB
KDTC
DTC Code
Φe (n)
(d)
FIGURE 8: Various SPLL and SSPLL topologies. (a) An integer-N SSPLL. (b) A fractional-N
analog SSPLL. (c) A fractional-N analog SPLL. (d) A fractional-N digital SPLL. FCW: frequency
control word; BBPD: bang-bang PD.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
51
DSM
FCW
TDC
ADC
DLF
MMD
CKVCO
BBPD
DCO
DSM
FCW
SPD
Vref
Vsmp
GM
+
-
CKVCO
Vctrl VCO
DSM
FCW
Vsmp
Vref
CKREF Leads
PLL [26]. The 5.5-7.3-GHz PLL is implemented
in a 28-nm CMOS technology
and achieves 75-fs RMS jitter and a
-249.7 dB FoM, with a 52-MHz crystal
reference. It is further cascaded by a
frequency tripler to generate an RF
LO and then divide by two to obtain
Vctrl VCO
Vctrl VCO
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