IEEE Solid-States Circuits Magazine - Fall 2021 - 54

polarity data so that LMS-based digital
calibration loops can be used. In addition,
an FLL loop is also included to
reduce the PLL locking time. This hybrid
approach leverages the benefits
of SPDs, digital calibration, and a PFD
CP loop to obtain a high-performance
fractional-N PLL.
Phase Detection Circuit Design
Although fractional-N SPLLs have demonstrated
sub-100-fs RMS jitter, there
are still some performance gaps compared
to integer-N PLLs (see Figure 6).
This is mainly due to the extra random
jitter, QN, and power consumption introduced
by the DTC [25]-[31]. Moreover,
similar to other PD topologies,
e.g., the CP in a classic analog PLL and
the TDC in a DPLL, the nonlinearity of
the DTC circuit results in fractional
spurious tones and noise folding, contributing
a significant amount of integrated
jitter, especially at near-integer
channels [43]. Despite the PD topology,
a wide linear operation range is
needed to handle the accumulated
phase QE at the CKFB due to DSM.
Figure 11 compares a TDC and
a DTC used as a PD. A classic TDC is
implemented as a delay line, and its
resolution is limited by the singleinverter
delay, which is ~10 ps in a
28-nm CMOS process. On the contrary,
a DTC can easily achieve a 100-fs delay,
which is an order of magnitude
smaller. Thus, the DTC has become a
more popular choice in recent years,
due to its fundamentally superior QN
over the TDC. Many techniques have
been proposed in the literature to reduce
the TDC resolution, at the cost of
increased design complexity and even
power and area penalties, e.g., a noiseshaping
TDC [48], [49], coarse-fine
TDC [16], [50], timing amplifier-based
TDC [51], Vernier delay line-based TDC
[52], and so on.
Nondoubler Mode
97 fs
Doubler Mode
75 fs
Digital
DTC
MMD
SPD, GM,
LF, FLL
0.6 mm
VCO
(a)
For DTCs, there are two major circuit
topologies, as conveyed in Figure 12.
The first is an RC delay-based DTC,
otherwise known as a variable slope
DTC [see Figure 12(a)] [53]. It consists
of an RC delay core and an inverter
buffer that acts as a voltage comparator.
The DTC code controls the n-bit
switched-capacitor bank to realize a
unit delay of
a total delay range of T2 res
n
TRC2
$
resLSB
= ln
$
$
and
. This
(b)
FIGURE 10: (a) A measured PLL PN at a fractional-N channel (6.33 GHz) and (b) PN spectrum
measured at a 28.5-GHz Tx output [26].
54
FALL 2021
IEEE SOLID-STATE CIRCUITS MAGAZINE
topology is commonly used in DTCbased
SPLLS and SSPLLs [25]-[31] for
its simplicity and ability to operate
with a low supply voltage (e.g., 0.8 V).
For example, in the PLL in Figure 9, a
10-b DTC with a 650-fs resolution is
used to support the VCO frequency of
5-7 GHz for a second-order DSM. The
resistor programmability covers the
process variation, which can be calibrated
if needed. Although this DTC
topology is simple, it is not trivial to
achieve a PN floor below -160 dBc/
Hz and an integral nonlinearity (INL)
of ~1 LSB [26], [29], [43], [53], which
is typically required for an ultralowjitter
PLL (i.e., sub-100-fs RMS jitter).
DTC PN is code dependent (it is
worst at the maximum code), and the
two major contributors are the core
delay stage and inverter buffer. The
0.4 mm
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