IEEE Solid-States Circuits Magazine - Fall 2021 - 55

TABLE 2. A PLL PERFORMANCE SUMMARY AND COMPARISON TO STATE-OF-THE-ART FRACTIONAL-N PLLS.
Technology
Type
fREF (MHz)
fout (GHz)
RMS jitter
(fs)
Fractional
spur (dBc)
Reference
spur (dBc)
Power (mW)
FoM (dB)
Area (mm2)
JSSC 2016 [29]
28 nm
Subsampling,
analog, and
type 2
40
11.72
176
(10,000 to
40 million)
Less than -56.6
-69
5.6
-247.6
0.25
ISSCC 2016 [28]
28 nm
Sampling,
digital, and
type 2
40
5.825
159
(10,000 to
40 million)
Less than -54
-78
8.2
-246.8
0.3
JSSC 2017 [16]
14 nm
TDC, digital,
and type 2
26
2.69
137
(10,000 to
10 million)
Less than -78.6
-87.6
13.4
-246
0.257
ISSCC 2019 [36]
28 nm
PFD CP,
analog, and
type 2
40 × 4/80 × 2
5.825
110/82
(10,000 to
10 million)
Less than -60
-73.4/-66.4
22.8/14.7
-245.6/-250
0.47
JSSC: IEEE Journal of Solid-State Circuits; ISSC: International Solid-State Circuits Conference.
*Dual-core VCO mode.
single-sideband PN of a DTC due to
its delay core was derived in [26] and
[53], in which, for simplicity, only thermal
noise is considered. The PN at the
midcode is given in (2), which defines
the minimum CLSB required to achieve
a certain PN floor for a given Tres, fREF,
and number of bits, n. For example,
Tres = 650 fs, fREF = 104 MHz, n = 10 b,
and CLSB = 2 fF results in a PN of roughly
-171 dBc/Hz due to the delay stage,
which is sufficiently low not to dominate
the entire DTC noise floor.
L
,
10 log10 2kT fREF$$ 2
; cmr 2 2 T 2
n
$
$
ln2
C
LSB
res
E
(2)
Instead, the inverter buffer is dominant
due to its slow input slope.
Thus, the inverter buffer is typically
sized up to a few hundreds of
micrometers in width to reduce
the amount of flicker and thermal
noise contributing to the output
clock jitter.
As to the DTC nonlinearity, the
slope-dependent (i.e., code-dependent)
propagation delay due to the
inverter buffer, Δtcmp, is the main
cause of the nonlinearity in an RC
TDC
=
ADC
CKFB
delay-based DTC, as illustrated in Figure
12(a)
[29]. It typically results in
DTC INL. For differential nonlinearity
(DNL), it is dominated by the matching
of the capacitive array. Since the CLSB
required to meet PN requirement is
~2 fF, it is large enough to obtain good
matching and thus little DNL (e.g.,
±0.2 LSB). To improve the INL, a fixed
capacitor can be paralleled to the tunUnit
Delay τ
CKREF
DQ
Q1
DQ
Q2
+
TDCout [n:0]
DTC
=
DAC
C
CKREF
Vdly
CKFB
CKREF
CKDTC
CKDTC
τ TDC
FIGURE 11: The TDC versus the DTC used for phase detection in a PLL.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
55
DQ
Qn
ing capacitor bank to reduce the input
slope variation across the code. Since
an oversized inverter buffer is required
for PN anyway, it also provides
significant fixed-capacitive loading to
improve the INL.
In addition to static distortion,
code-dependent supply settling errors
also contribute to INL [see Figure 12(a)].
The DTC draws a large amount of
ISSCC 2020 [27]
28 nm
Sampling,
analog, and
type 1
500
12.47
58.2
(1,000 to
100 million)
Less than -63.9
-73.5
18
-252.1
0.16
ISSCC 2021 [31]
14 nm
Sampling,
analog, and
type 2
76.8 × 2
3.1
89*/91.5
(10,000 to
40 million)
Less than -72.4
-72
14.2*/8.2
-250.4*/-251.6
0.31
PLL IN
FIGURE 9,
JSSC 2019 [26]
28 nm
Sampling,
analog, and
type 2
52 × 2
6.33
75
(10,000 to
10 million)
Less than -64
-70.2
18.9
-249.7
0.45
τ TDC
CKREF
Q1  1
Q2  1
Q3  0
IEEE Solid-States Circuits Magazine - Fall 2021

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