IEEE Solid-States Circuits Magazine - Fall 2021 - 59

Instead, a wide tuning range, low power
consumption, and a compact layout
are the main considerations. The authors
of [4] provide a good summary
of various frequency tuning techniques
for mm-wave VCOs, including
switched-capacitor, switched-inductor,
and transformer-based coarse- and
fine-tuning techniques. The state-ofthe-art
design reported in [67] demonstrated
a continuous tuning range
from 18.6 to 40.1 GHz (i.e., a 73.2%
tuning range), with 15 mW of power
consumption in a 40-nm bulk CMOS
process, by employing multiple tuning
techniques. The achieved VCO PN
across the tuning range is better than
-100 dBc/Hz at a 1-MHz frequency
offset, which is typically sufficient for
use in a frequency multiplier.
Frequency Multiplier Design
The frequency multiplier is another
critical building block for 5G LO generation
(see Figures 4 and 5). It helps
to lower the operating frequency of
the fractional-N PLL for optimal PN
and enables multiband support by using
different multiplication factors. An
SSPLL can be used as a frequency multiplier,
as illustrated in Figure 15 [6].
In this design, the first PLL is a 7-GHz,
PFD CP, fractional-N PLL, followed by
an SSPLL to achieve multiplication by
four. Quadrature VCOs were used in
the SSPLL to obtain I/Q outputs for the
homodyne transceiver. The entire LO
generation circuit achieved sub-100-fs
RMS jitter, with 27 mW of power
consumption. The bandwidth of the
SSPLL was set higher than 100 MHz to
suppress the PN of the 28-GHz VCO.
Consequently, the RMS jitter of the
multiplier output was close to the RMS
jitter of the 7-GHz PLL. The topology
in Figure 15 is also known as a cascaded
PLL, which is an effective way
to obtain low jitter for mm-wave LO
generation. In general, an integer-N
PLL can be used as a frequency multiplier.
Moreover, a divider could be
added in the CKREF path before the PD
to synthesize a multiplication factor
of M/N (M and N are integer numbers).
Another commonly used topology
is an injection-locked frequency multiplier
(ILFM) [21], [39]-[41]. In ILFMs,
instantaneous phase variations of a
free-running VCO are naturally corrected
by periodically injected reference
signals. Due to this intrinsic
phase realignment mechanism, ILFMs
can generate precise clock signals
28-GHz
Quadrature LO
QPLL
CKREF
CKFB
Up
PFD
Down
7 GHz
I
÷ 2
Q
Phase Code
DSM FCW
×4
FIGURE 15: The block diagram of a 28-GHz quadrature fractional-N synthesizer based on
a cascaded PLL [6]. QPLL: quadrature PLL; QVCO: quadrature VCO; SHPD: sample-and-hold
phase detector; V2I: voltage-to-current converter.
÷ 2
7 GHz
Pulse
Generator
I
Q
VI
LF
QPLL
OUT15_I ± (25-30 GHz)
INJ15_I±/Q±
EN15
Pulse
Generator
4
CKREF
PFD + CP + LF
3-4 GHz
÷ N
FCW
DSM
Fractional-N PLL
EN15
4
Pulse
Generator
INJ3_I±/Q±
FIGURE 16: A single-PLL-based multiband 5G LO generator using ILFMs [39].
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
59
ILFM_X3
OUT3_I ± (5.2-6 GHz)
INJ3_I+
4
÷ 2
INJ15_I+
OUT15_Q+
OUT15_Q-
OUT3_Q-
OUT3_Q+
FTL
+
-
ILFM_X15
IEEE Solid-States Circuits Magazine - Fall 2021

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