60 FALL 2021 IEEE SOLID-STATE CIRCUITS MAGAZINE PHR_I 20 GHz + 60 GHz CKREF DTC CKDTC TDC - Buffer (1-PHR_F).KDTC Asynchronous Counter FCW PHR_F Σ PHR_I CKDTC (a) VDD M2 CP To 60 GHz Positive Buffer To 60 GHz Negative Buffer LP MA To 20 GHz Positive Divider CS LS km MB Lsh To 20 GHz Negative Divider Csh CT CT LT 20 GHz Tank From Positive DCO M1 C1 C1 M1 VB1 M2 From Negative DCO CKVG Clock Gating CKR CKV CML÷4 CMOS÷2 M1 VB2 km1 M1 20 GHz C2 VDD C2 + DLF DCO 60 GHz 60 GHz Output Off-Chip Load km2 VT MT (b) (c) FIGURE 17: A 60-GHz LO generator using a 20-GHz DPLL with a third harmonic extractor [35]. (a) A 20-GHz PLL with a third harmonic extractor. (b) A 20-GHz class F DCO. (c) A 60-GHz buffer for third harmonic extraction. Vb: biasing voltage; CKV: variable clock (a divide down clock from DCO output); CKR: reference clock; CKVG: gated variable clock or gated CKV; CML: current-mode logic.