IEEE Solid-States Circuits Magazine - Fall 2021 - 73

Figure 6(a) shows the power consumption
of the CSC-AP versus clock
frequency for core voltages of 0.62
and 1 V. Within a range of the clock
frequency of 100 MHz, the core voltage
0.62 V is the minimum operational
voltage that delivers the minimum
power dissipation and highest efficiency.
Thus, we adopt this voltage
for sub-100-MHz frequency ranges
for low-power, high-efficiency applications.
Figure 6(b) shows the performance
and efficiency of the CSC-AP
that corresponds to (12) given the
power consumption at a core voltage
of 0.62 V.
With 16 MAC units operating at
100 MHz, the peak performance of
the accelerator reaches 3.2 GOPS.
The power dissipation and, consequently,
true efficiency of the
chip at a core voltage of 0.62 V
are approximately 74.3 mW and 43
(. /. )
CSC architectures, similar to butterfly networks,
can be categorized as one of the high-bandwidth
communication networks for parallel system
interconnections.
compression 18411c
(as in the
compressed LeNet-300-100), the
equivalent performance and efficiency
of the chip range between
3.2 GOPS and 43 GOPJ for an FC
layer where
c 1= and 268.8 GOPS
and 3.6 TOPJ for a highly compressed
CSC layer where
respectively.
c 84 ,=
=32 0074 GOPJ. The true performance
and power consumption
of the hardware are agnostic toward
the compression rate of the CSC
layer it implements. In other words,
the chip implements a CSC layer
with the same actual performance
and power consumption regardless
of what N, F, or D are in (11).
As a result, given a CSC layer with
Place-and-Route Physical Design
CSC-AP
3.7 mm
The Fabricated Die
CSC-AP
Unpackaged
(a)
(b)
(c)
FIGURE 5: (a) The post place-and-route physical design and actual fabricated die of the CSC-AP. (b) The packaged die compared to the size
of a U.S. quarter coin. (d) The test, verification, and measurement setup, highlighting a dual-tracking voltage supply to power up the chip
mounted on a printed circuit board (PCB). A VC707 platform is used to drive the chip with test benches and signals using a field-programmable
gate array mezzanine card (FMC) high-pin-count cable; a multimeter and an oscilloscope are employed for signal monitoring and
measurement.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
73
Packaged Die (Chip)
Precise
Power
Chip + PCB
VC707
Related Work and Comparison
Deng et al. [6] proposed PermDNN,
which is an approach to customizing
sparse weight matrices with a
diagonalization scheme, for which
they designed a 32-PE (256-multiplier)
accelerator with 16-b precision
dataflow synthesized in 28 nm and
operating at 1.2 GHz. At first glance,
the CSC layers look similar to the
permuted diagonal matrices in the
PermDNN. However, in PermDNN, a
weight matrix is chunked into many
smaller diagonalized matrices, and
the connectivity of consecutive layU.S.
Quarter
Core A
Core V
I/O A
I/O V
Scoped Clock
ers as a tweakable parameter is not
defined, whereas a CSC layer uses
one continuous diagonalized (cyclic)
weight matrix per layer, the
cascade of a few of which guarantees
the full connectivity between
alternate layers.
CIRCNN [7] is another similar
work to the CSC layers in which a
weight matrix in a DNN is partitioned
into K-by-K submatrices,
each of which, due to their circulant
structure, can be defined with
only K scalars, thus compressing
the model by K times. The convolution
operation of the block-circulant
matrices can be efficiently performed
using FFT, elementwise matrix
multiplication, and inverse FFT
operations. The authors of CIRCNN
also proposed an accelerator whose
synthesis results in 45 nm and
200 MHz and shows an equivalent efficiency
of nearly 10 TOPJ. Despite
its significant complexity reduction
FMC
1.9 mm

IEEE Solid-States Circuits Magazine - Fall 2021

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