IEEE Solid-States Circuits Magazine - Fall 2021 - 79

replicated logic, packaging cost is
higher, and there is additional design
effort and complexity. Flexibility and
modularity as described in [3] hints
at combining smaller functions to
build larger ones, and we see the rise
of heterogeneity in the 2000s and
2010s. For example, the embedded
multidie interconnect bridge (EMIB)
to enable die-to-die integration onpackage
was patented by Intel in
2008, and the ideas were published
in 2011 [9], [10]. Additional information
on EMIB will be provided later in
this article. In the " Disparate Process
Technology Requirements for New
Applications " section, the need for
heterogeneity from a process technology
perspective is summarized.
Disparate Process Technology
Requirements for New Applications
As mentioned in the " Moore's Law and
Path to Heterogeneity " section, communications,
computation, and intelligence
are converging to provide
the ability to intelligently distribute
high-performance compute tasks
from a single edge device to high-performance
compute engines that sit
on network platforms. For example,
the nearest access point or base station
may also double as a high-performance
compute platform. If we go
down the path of monolithically integrating
input-output (I/O) (wireless,
optical, electrical) with digital compute
and memory, it will lead to suboptimality
in the radio frequency (RF)
and I/O devices. As we can see from
Figure 2, the requirements for digital,
RF, and I/O are all very different.
For example, digital processes are
optimized for density, leakage, and
speed, whereas radio-frequency integrated
circuits (RFICs) perform
better in a process that has been optimized
for passives, higher voltage,
and speed. Mixed-signal circuits tend
to require the best of both worlds.
Decoupling the RFICs, I/O ICs, and
digital ICs allows for separate roadmaps
and the ability to create highly
optimized circuits using specialized
process nodes and transistors. In the
next section, we review the past forDecoupling
the RFICs, I/O ICs, and digital ICs
allows for separate roadmaps and the ability
to create highly optimized circuits using
specialized process nodes and transistors.
ays into heterogeneous integration
necessitated by disparate technology
requirements for different applications,
starting with FPGAs.
FPGAs and Heterogeneous
Integration
The concept of partitioning chips is not
new. The rise of domain specific compute
platforms came in 1996 with a paper
by Abnous and Rabaey [7], where
they described a template architecture
that contained configurable logic,
memory, a configurable interconnect,
and specialized satellite processors. A
realization of this concept was shown
at the 2000 International Solid-State
Circuits Conference (ISSCC 2000) [8],
which used an embedded FPGA fabric
to support wireless signal processing
and speech recognition. This work
represented an order of magnitude
improvement over traditional digital
signal processors by exploiting locality
of compute and memory and distributed
control.
Prior to the FPGA-chiplet ecosystem,
FPGA providers started to monolithically
integrate processors and
transceivers to provide greater programmability
and functionality, creating
a system-on-chip (SoC) FPGA as
described in [11], where Altera FPGAs
combined a dual-core ARM Cortex
processor with an FPGA. In [12], ST
Micro presented a multimedia system
with an embedded FPGA, processor
core, memory, and configurable I/O
to implement image/speech processing
and recognition. The FPGA flexibility
provided multiple functions:
data path for processor, control for
bus coprocessor, and I/O control interface.
Measured speedups using
the system ranged from 1.6-10×.
Xilinx started experimenting with
integration of multiple dies on passive
interposer in early 2010s and shared
their results in two papers [13], [14].
They used " stacked silicon interconnect "
to connect FPGAs to multiple
wireline transceivers, other FPGAs,
and analog-to-digital converter/digitalto-analog
converter (ADC/DAC) arrays
to start interfacing FPGAs to the analog
world. A monolithically integrated
PowerPC core was also included. The
use of these silicon interconnect technologies,
either in package or on passive
interposer, enabled the ability
to extend FPGA functionality beyond
what was originally intended.
Density
Leakage
1
2
3
4
5
Speed
Logic/Memory
IO
RF
Mixed-Signal
High Voltage
Passive
FIGURE 2: The disparate technology requirements for different applications.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
79
IEEE Solid-States Circuits Magazine - Fall 2021

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