IEEE Solid-States Circuits Magazine - Fall 2021 - 80

The use of these silicon interconnect
technologies, either in package or on passive
interposer, enabled the ability to extend
FPGA functionality beyond what was
originally intended.
Technology innovation sometimes
arises from dire necessity. As Altera
moved to Intel's 14-nm process, the
transceivers were to remain on TSMC
process to enable maximum designreuse.
This meant that there was a
need to create transceiver chiplets that
could be copackaged with FPGAs,
and hence, in 2013, FPGAs became
the first products to use Intel's EMIB
packaging and assembly capabilities,
leading the 2.5D heterogeneous integration
revolution. The chiplet-enabled
FPGA was published in 2017 at
ISSCC [15], decoupling the transceiver
roadmap from the FPGA roadmap,
and allowing the FPGA and transceivers
to leverage the best technologies
for each of their purposes. Today,
EMIB is one of the key tools available
to designers that allow closer integration
of disparate dies on a package
using a high-throughput silicon
interface embedded in a package.
EMIB enables 0.5 pJ/bit I/O efficiency
between dies using microbumps and
denser I/O [7]. This is 3.4× better
than I/O in a standard package.
Heterogeneous Integration
for Wireless Systems
In recent advanced wireless research
test-chips, there are efforts both in
industry (e.g., Intel) and academia
[e.g., University of California, San Diego
(USCD)] to leverage modularity
and heterogeneity to integrate RFICs
with antenna arrays. For example, in
[16], UCSD has integrated an antenna
array on a quartz dielectric that is 3D
integrated with phased array millimeter-wave
(mm-wave) transceivers.
At Intel, in [17] an E-band 64-element
phased array transceiver is 3D-integrated
on-package with antenna elements.
When advanced packaging
technologies are not available in aca80
FALL
2021
demia, FPGAs combined with ADC/
DAC arrays and transceivers are integrated
at the board level to create
the required compute-communicate
platform for new and emerging applications,
as seen in the work published
in [18] by the University of
California, Berkeley.
3D Heterogeneous Integration
Heterogeneous integration with 3D
technologies has a long history.
Through-silicon via (TSV)-based
3DIC fabrication was proposed and
demonstrated in 1980s in Japan as
a part of an R&D program, " ThreeDimensional
Circuit Element R&D
Project " [19]. Subsequently, TSVs became
a prominent topic in academic
and industrial R&D centers. Many
pioneering prototypes were developed
at Tohoku University [20], [21].
Numerous fabrication flows and analytical
works followed for decades.
Initially, the 3DICs were focused on
flash memories and DRAM stacks.
IBM demonstrated a 3D DRAM prototype
[19] ahead of Micron's hybrid
memory cube (HMC) and Samsung's
high bandwidth memory (HBM). During
that same year Elpida shipped
four-stack 8-GB DRAM and Samsung
announced 32-GB 3D-DRAM.
Practical 3D image sensors started
becoming viable in the 2000s.
Toshiba, ST, and others commercialized
CMOS image sensors with
TSV electrodes. However, to the
best of our knowledge,
the first
demonstration of a commercial 3Dstacked
image sensor was by SONY
corporation in [19]. Subsequently
they demonstrated a three-stack
3DIC [20]. Apple has extensively
used packaging-based 3D integration
in their mobile products. A11
application processor was integratIEEE
SOLID-STATE CIRCUITS MAGAZINE
ed with DRAM using integrated fanout
(InFO) [21].
Recently, IEEE has provided a vision
for the electronics industry to
identify future challenges and potential
solutions relating to heterogeneous
systems integration. This
primarily arises from the fact that the
traditional way of interpreting Moore's
Law shows a slowdown in technology
scaling. However, the heterogeneous
aspect of Moore's Law shows that
leveraging modularity and flexibility
can in fact extend Moore's Law in
multiple dimensions. In the following
section, an introduction to the heterogeneous
integration roadmap is
provided along with formalized definition
of terms that are used across
the semiconductor industry today in
the context of heterogeneous integration
technologies.
Heterogeneous Integration
Roadmap and Technologies
The IEEE heterogeneous integration
roadmap (2019 and 2020) provides
a vision for the electronics industry
and identifies future challenges
and potential solutions that relate
to system integration technologies.
The roadmap provides the following
definition: " heterogeneous integration
refers to integration of separately
manufactured components into a
higher-level assembly that, in aggregate,
provides enhanced functionality
and improved operating characteristics. "
Three main technologies have
been identified for heterogeneous integration:
1) system-in-package (SiP),
2) wafer-level packaging (WLP), and
3) 2D and 3D interconnects. SiP technologies
are well understood in
the modern world and are well-established,
creating a trillion-dollar
global electronics market [29]. The
most common example of an SiP is
the mobile smartphone application,
which has adopted heterogeneous
integration effectively and exemplifies
Moore's prophecy. The mobile
phone form factor incorporates
the most advanced node processor
and memories in close proximity
to older technologies that provide
IEEE Solid-States Circuits Magazine - Fall 2021

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