IEEE Solid-States Circuits Magazine - Fall 2021 - 85

Future Innovations and Summary
The previous sections have highlighted
innovations in 2.5D and 3D
heterogeneous integration and new
products and technologies that are
available to designers to push the
limits of design in the future. The
new 2.5D/3D design tool kit can be
leveraged to create new computecommunicate
platforms for the future
that incorporate intelligence.
We are already seeing recent examples
of exciting research coming
out of industry, academia, and government
research programs. For example,
in a recent IEEE Micro article
[38], Ayar Labs and Intel presented
high-throughput terabits/s optical
transceiver chiplet integrated
on-package with an FPGA, enabling
new compute-communicate architectures
that require very highthroughput
I/O for intelligence at
the edge applications. The optical
I/O chiplet is fabricated in a specialized
Global Foundries 45-nm process
node for optical ICs.
As we approach wireless systems
beyond 5G and look to 6G operating
at frequencies above 100 GHz, a
platform that supports high-energy
efficiency, wide range, and can support
multiple users simultaneously
providing terabits per second bandwidths
is impossible without the use
of heterogeneous integration technologies.
For example, if we want to
operate at 140 GHz, using a 16 QAM,
with required 8-Gbps throughput, the
chip-to-chip I/O will exceed 10's of
GHz, and will be exasperated at the
interface between the digital and RF,
where for each 2-GHz I/Q channel,
there will be on the order of 6-10 bits
being transferred at 2 GS/s, resulting
in up to 20 Gbps per I/Q channel. As
we increase frequency, bandwidth,
and modulation, the I/O and power
problem is exacerbated. In terms of
power, Intel's recent VTC 2019 paper
[39] conducted a detailed study of
the extent of the problem of the I/O
between the digital and RF at E-band
(60 to 90 GHz). Using their estimated
figure of merit for the best possible
chip-to-chip I/O interface (~2 pJ/bit)
The Stratix 10 FPGA was the first product to
utilize Intel's EMIB technology, which is used as
a passive die-to-die interconnect, similar to a
passive silicon interposer.
as a starting point, we can estimate
that for the E-band system, the power
attributed just to the I/O between
the digital and RF, will be 3 W for a
16-element, 16-user multiple-input,
multiple-output array. As we increase
the number of elements to 128, the
expected interface power jumps to
>20 W. As one can see, the I/O power becomes
the major bottleneck in terms
of power as the array size increases
and is further exacerbated at subTHz
(140 GHz) with over 1000 array
elements. Using EMIB integration, the
I/O power between the RF and digital
can be potentially reduced by 6# and
using Foveros, it can be potentially
reduced by 13#. Figure 8 shows such
a system concept leveraging both
EMIB and Foveros. There are multiple
challenges and potential advantages
to creating a system. One is antenna
FIGURE 7: Intel's Ponte Vecchio high-performance GPU for high-performance computing applications
utilizes both EMIB 2.5D interconnect and Foveros 3D interconnect
DSP/ML
Micro-3D
Nano-3D
Macro-3D
Micro-3D
Nano-3D
Package Substrate
Macro-3D
Memory
ADC/DAC
RFIC
Antennas
FIGURE 8: A conceptual drawing of 3D integrated RF, analog, mixed-signal, and digital
circuits for sub-THz 6G platforms.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
85

IEEE Solid-States Circuits Magazine - Fall 2021

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