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About the Authors
Farhana Sheikh (farhana.sheikh@
intel.com) received her Ph.D.degree
from the University of California,
Berkeley in 2008. She is a senior staff
scientist in Intel's Programmable Solutions
Group CTO and Strategy Office,
Hillsboro, Oregon, 97124, USA,
since 2018 and was at Intel Labs from
2008 to 2018. Her research focuses
on 2D/3D multidie heterogeneous integration,
millimeter-wave, and THz
massive multiple-input, multipleoutput
circuits, wireless control for
quantum computers, and intelligent
compute-communicate architectures.
She has published 48 papers
and filed 22 patents in the field of
solid-state circuits and is corecipient
of two prestigious International
Solid-State Circuits Conference Lewis
Awards for Outstanding Paper (2012,
2019) and is an IEEE Journal of Solid-State
Circuits guest editor. She
serves on multiple Solid-State Circuits
Society conference technical
program committees.
Ramune Nagisetty (ramune.nagi
setty@intel.com) received her B.S. degree
in electrical engineering from
Northwestern University and her
M.S. degree in electrical engineering,
specializing in solid-state physics,
from the University of California,
Berkeley. She is a senior principal
engineer in Intel's Technology Development
Group, Hillsboro, Oregon,
97124, USA. Most recently, she led
work in using chiplets and packagelevel
integration to reduce overall
portfolio cost, scale innovation, and
speed time to market. She joined Intel
in 1995. She has authored 11 technical
publications and has 15 issued
or pending patents related to process
technology and usage models. Her vision
of an industry-scale chiplet ecosystem
has been featured in Wired
Magazine and IEEE Spectrum.
Tanay Karnik (tanay.karnik@
intel.com) received his Ph.D. degree
from the University of Illinois Urbana-Champaign
in 1995. He is a senior
principal engineer and director
of Heterogeneous Platforms Lab of
Intel Labs, Hillsboro, Oregon, 97124,
USA. Previously he was director of Intel's
University Research Office. His
research interests are in heterogeneous
integration, small form factor
systems, 3D architectures, variation
tolerance, power delivery, and architectures
for novel devices. He has
published over 90 technical papers
and has 95 issued and 35 pending
patents. He received an Intel Achievement
Award for pioneering work on
integrated power delivery. Tanay is
a Fellow of IEEE and an International
Symposium on Quality Electronic Design
fellow, associate editor for IEEE
Transactions on Very Large Scale Integration,
senior advisor of the IEEE
Journal on Emerging and Selected
Topics in Circuits and Systems, and
a guest editor for the IEEE Journal of
Solid-State Circuits.
David Kehlet (david.kehlet@intel
.com) received his B.S. and M.S. degrees
in electrical engineering from Stanford
University. He is a researcher
at Intel, San Jose, California, 95134,
USA, working on pathfinding for
field programmable gate arrays
technology. He is currently developing
chiplets and interfaces to enable
a new model of electronic system
development. Earlier at Intel, he was
vice president of IP Engineering,
developing communications protocols,
signal processing, and memory
interfaces on Intel's programmable
logic devices. Recently, he represented
Intel regarding chiplet technologies
to the U.S. government, to
industry, and to Intel customers
and partners. He holds 18 patents
in the areas of computer graphics
and video.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
87

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IEEE Solid-States Circuits Magazine - Fall 2021

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2021