IEEE Solid-States Circuits Magazine - Fall 2021 - 9

pair, as shown in Figure 4(a). It can
be readily proved that the circuit's
transfer function, () /,
=
outin
given by
()
Hs =
where gm
RC sg R
gR RC s
mD SS
tance of M1
-+
SS ++ mS
()
/
12
1
,
(1)
denotes the transconducand
M2
and channellength
modulation is neglected. The
stage exhibits a zero and a pole,
respectively:
||
z
p
~ =
||
~ =
RC
1
+
(2)
SS
12
RC
gR
SS
mS
/
,
gR gR /)
mD 12 at
mD
/( + mS
(3)
For example, two stages lower the
and the magnitude of its response
varies from
low frequencies to gR at high
frequencies [Figure 4(b)]. The circuit
thus provides a boost factor of
gR /.
+ mS
pole frequencies are separated by
the same factor.
The CTLE stage of Figure 4(a) merits
two remarks. First, the boost factor trades
with the low-frequency gain (also called
the dc gain),
gR gR /).
mD 12 We
/( + mS
wish to maintain this gain around
unity so that the received data swings
are not attenuated. With low supply
voltages and channel-length modulation,
the boost factor typically
does not exceed 6 dB. Second, we
surmise that
~ p
should be placed
roughly around the Nyquist frequency,
but as indicated by the red plot in
Figure 4(b), the limited bandwidth
at the output makes it difficult to do
so. For this reason, high-speed CTLEs
often employ inductive peaking.
The output pole, 0~ , in Figure 4(a)
results from the load resistance
and capacitance, presenting significant
challenges in high-speed
CTLE design. The relative magnitudes
of this pole and that due to
source degeneration lead to different
responses and dependencies
upon CS
if ~~2 then increasing CS
p ,
RS
CS
(a)
FIGURE 4: (a) A basic CTLE stage and (b) its approximate response.
|H(jω)|
gmRD
CS
. As shown in Figure 5(a),
simply
shifts the high-pass response
to the left. On the other hand, if
p
gR .mD Second,
~~1 [Figure 5(b)], then two effects
emerge. First, ||H fails to reach its
maximum value of
1 +
gmRD
gmRS
2
ωz
(a)
1 +
gmRD
gmRS
2
ωp ω0 ωωω0 ωp
(b)
ωz
FIGURE 5: The CTLE response for (a) ~~2 and (b) ~~1 p .
p
IEEE SOLID-STATE CIRCUITS MAGAZINE
FALL 2021
9
|H(jω)|
gmRD
CS
1 +
gmRD
gmRS
2
ωz
(b)
ωp
ω
RD
Vout
Vin
M1
M2
RD
VDD
12 Note that the zero and
Pole-Placement Considerations
In the CTLE stage studied previously,
we may naturally conclude that the
degeneration pole, p~ , should be placed
around the Nyquist frequency. In realbandwidth
by 35%. These constraints
imply that it is difficult to use more
than two CTLE stages, and that the
DFE in Figure 2(a) must shoulder the
remainder of the equalization.
BW =- (4)
tot
21f
1/n
.
|( p)| 2
Hj~ =+ 1
1
K 1
2 > cm+
gR
2
mS
2
That is,
|( )|
p
2 H
.
(6)
a greater C1 and hence a lower ~ p
Hs VV is
reduce the frequency at which the
peak occurs. These points encourage
us to apply inductive peaking
so as to approach the first case.
To raise the boost factor, we can
cascade multiple CTLE stages, but
at the cost of reduced small-signal
bandwidth and greater power consumption.
If each stage's bandwidth
limitation is approximated by a single
pole at
2 f ,0r then n identical stages
yield a total bandwidth of
=
ity, however, the situation is more complex.
With the low available boost factor
per stage, the Bode plot of |( )|Hj~ in
Figure 4(b) proves inaccurate because
~ z
~
and p~ are separated by a factor
of only 2 to 3. The actual behavior is
depicted in Figure 6 and can be quantified
as follows. We express |( )|Hj 2
from (1) as
|( )|
Hj~
p
22 z
= K
~~
~~
2
2
+
+
12
2
2
,
(5)
where Kg ,RmD and evaluate it at
~~pm Sz~ (/ ):gR== +
Hj~ =+ 1
K
2 cm+
gR
1
1
mS
mS
2
If the boost factor,12
2
.
(7)
+gR /, ranges
from 2 to 3, then |( )|Hj p~ falls between
0.79K and 0.74K, i.e., roughly 2 to 2.5 dB
below the maximum value. The key
|H(jω)|
gmRD
IEEE Solid-States Circuits Magazine - Fall 2021

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