IEEE Solid-States Circuits Magazine - Winter 2022 - 14

is around 30 fF .0 With these typical
numbers, let us now explain the read
and write operations for an example
cell at the intersection of WL1 and
BL3 as highlighted in Figure 2.
Upon raising WL1, we expect the
storage node of this cell to begin
charge sharing with BL3 to produce
a voltage indicative of whether the
stored data are a 0 or a 1. To see
this clearly, consider the voltage levels
of the cell capacitor at the time
of reading to be either V1
(for the
stored 1) or V0 (for the stored 0). We
note that V1
and V0
may not be 1V
and 0 ,V respectively, at the time of
reading due to the charge leakage
over time through the access transistor.
voltage
level of V1
charge with CBL
^
+ BL
If a cell capacitor holding a
or V0 shares its
is
(assuming CBL
discharged initially),
^
^ Ss1
it will gen+
BL
erate either CV CC hh or
^ Ss0
CV CC hh on the BL. The task
that remains now is to determine,
with the aid of an SA at the bottom of
the array, whether the voltage developed
on the BL is above or below our
reference voltage, ideally midway
between the voltage levels produced
by a 1 and a 0. This simple task of
generating a refence voltage poses
several challenges; we will explore
these challenges here before arriving
at a solution.
The first challenge is to produce
a reference voltage that tracks the
values of V1
and V0 at the time of
read. A fully charged cell capacitor
leaks its charge over time to
the substrate through the junction
of the access transistor. Similarly,
a fully discharged cell capacitor
may accumulate charge over time
from the BL due to the subthreshold
operation of its access transistor.
In fact, a cell capacitor may lose
close to half of its charge in under
100ms This necessitates any reference
voltage to also follow a similar
change in time. It is possible
to accomplish this through clever
design, but as we will see later, it
will not be necessary.
The second problem is that the
.
voltage developed on the BL, corresponding
to either 0 or 1, has a
common-mode voltage close to
Even in the ideal case of V 1V1
and V 0V0
=
=
0 .V
,
, the voltage developed
on the BL is either 91mV or 0 ,V
having an average (common-mode)
voltage of about
45 .mV This low
common-mode voltage may not be
the best bias level for the comparator
or the SA we wish to design. For
example, a simple inverter offers its
maximum gain at a bias voltage of
around
05 . V (assuming a 1V supply).
So, we need to find a mechanism
to level shift the BL voltage to
around this desired level.
The third problem is that once
BL0 BL1 BL2 BL3
WL0
WL1
WL2
WL3
Ref SA SA SA SA
FIGURE 2: A preliminary architecture for a 2D array of memory cells.
a memory cell is read, i.e., after its
stored charge is shared with the BL,
the data in the cell is destroyed (at
least weakened due to sharing) and
we must find a way to restore this
data. The read operation is indeed
destructive and must be followed by
a restore operation.
The fourth problem is that if we
CS
leave a memory cell unaccessed for
a while (~
100ms),
it will lose its
data due to the leakage current we
mentioned earlier. This means that
we must have a way to periodically
read the entire memory to restore or
to refresh its data.
At this point, the readers are invited
BL0 BL0 BL1 BL1
WL0
WL1
WL2
WL3
SAP
SAN
SA
SA
FIGURE 3: A folded-BL architecture for a 2D memory array.
14 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
to think about these four problems
before reading further.
Let us now see how all of these
CS
problems can be addressed by using
a folded-BL architecture, as shown
in Figure 3. In this architecture,
half of the cells at the intersections
of WLs and BLs are removed. As a
result, when a WL is selected, only
half of the BL (either BL or
BL )s are
connected to the storage nodes; the
other half will serve as the reference
voltages for the SAs. For example, by
selecting WL0, BL0 and BL1 access
the cells while BL0 and BL1 serve
IEEE Solid-States Circuits Magazine - Winter 2022

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