IEEE Solid-States Circuits Magazine - Winter 2022 - 46

80
70
60
50
40
30
20
10-8
10-9
10-10
10-11
10-12
10-13
100
101
fs = 2fin [GHz] (Speed)
(a)
Tech ≥ 32 nm:
Tech ≤ 32 nm:
(TI-) SAR
(TI-) SAR
(TI-) Pipe
(TI-) Pipe
(TI-) PipeSAR
(TI-) PipeSAR
102
20
30
40
50
60
SNDR at fin [dB] (Accuracy)
(b)
(TI-) Flash
(TI-) Flash
Others
Others
FIGURE 1: State-of-the-art design of various ADC architectures (data from [1]): (a) accuracy-speed, and (b) accuracy-energy.
whereas accuracy encapsulates both
aggregate and effective resolution.)
The fundamental limits of elementary
building blocks, some of which
have been analyzed by [2] and [3],
and form the basis of our framework,
are enhanced by architectural
overheads and process effects, and
serve as a valuable guideline when
starting a new design and/or changing
process nodes. The presented
analysis collectively captures architectures,
variants, and contributions
not shown in previous literature and
includes process effects beyond the
typical supply scaling.
Our investigation starts by examining
the state-of-the-art standings
with data from [1], shown in Figure 1.
Flash, successive approximation
register (SAR), pipeline, pipelinedSAR,
and other (,TR time-based) architectures
are included, with their
time-interleaved counterparts, and
an older/newer-than 32-nm CMOS
process node distinction. One can
notice that the architectures that are
most widely used across a wide range
of specifications are the SAR and the
pipeline, while there is a recent emergence
of the pipelined-SAR. A comparison
of the accuracy-speed data
points after first-order curve fitting
[Figure 1(a)], places the pipeline as
the winner for combined high accuracy
and speed. The time-interleaved-
SAR is the leader in absolute speed
for medium accuracy, while its speed
has benefited more than the pipeline
from technology scaling. The pipelined-SAR
is on par with the pipeline
in accuracy while approaching similar
speed levels. The flash mainly resides
at lower accuracies owing to its
hardware-intensive nature. The accuracy-energy
data points [Figure 1(b)]
reveal that the SAR is leading in efficiency
for medium-to-high accuracies,
while the pipeline can achieve
higher absolute accuracy levels. The
efficiency of both architectures has
improved with technology scaling,
while the SAR shows an increasing
trend of moving to lower accuracy
and higher speed. The pipelined-SAR
demonstrates the efficiency of the
SAR while approaching the accuracy
levels of the pipeline. This hybrid
benefits from technology scaling as
well since most of the designs are
implemented in advanced-process
nodes. The flash shows an efficiency
that is similar to that of the SAR, that
is, in the low-accuracy regime.
It is worth noting that these early
Vin
-
-
S/H
+
+
2B-1
B
Thermometer-to-Binary Encoder
FIGURE 2: A B-bit flash ADC (the S/H is optional).
46 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
Dout
+
+
-
-
conclusions are a mere interpretation
of the published data, which, as
already stressed, does not provide
a complete picture of architectural
limits and capabilities. The introduced
framework is an attempt to
shed some light on how fundamentally
sound this interpretation may
be. To this end, the key architectures
highlighted above are first briefly reviewed
prior to deriving their accuracy-speed-power
limits.
70
80
SNDR at fin [dB] (Accuracy)
P/fs [J] (Energy)
tjit = 50 fs
IEEE Solid-States Circuits Magazine - Winter 2022

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