IEEE Solid-States Circuits Magazine - Winter 2022 - 47

Flash Accuracy-Speed-Power Limits
The flash ADC (Figure 2) relies on a
full parallelism to quantize a signal
in a single-clock cycle [4], [5]. For
B-bits, it comprises 21B
to simultaneously compare the input
signal with 21B
power consumption, including sampler,
comparator, ladder, and digital
logic (encoder) contributions
- comparators
- equally spaced
reference levels, given by a resistive
ladder. Each comparator evaluates
the difference between the input
and its corresponding reference tap,
outputting a thermometer code of
digital 0s and 1s. A thermometerto-binary
encoder translates the
resulting thermometer word into
the final binary format at the ADC
output. Because of their parallelism,
flash ADCs achieve the highest
speed among single-channel architectures.
Their speed is limited by
the comparator and encoder delays.
The comparator regenerates exponentially
on an input [3] with a time
constant
x Lm=Cg
the comparator output
load and
gm the latch transconductance. x
depends on the process cutoff frequency
,fT
which typically increases
with scaling to finer-process nodes
[6]. Thus, the flash architecture theoretically
benefits from scaling, as
seen in Figure 1(a). Further, owing to
its minimal latency, flash is a good
candidate for feedback systems.
However, the exponential comparator
increase with B sets an upper
bound on resolution. For each added
bit, the comparator number doubles
while requiring twice the accuracy. For
a noise-limited design, this leads to a
4×-power for each comparator and a
total of 8×-power for the ADC. Aside
from that, the increasing nonlinear
capacitive load to the input results in
bandwidth loss and signal-dependent
distortion. To date, full flash converters
are limited to 8 bits. Another issue is
the multicomparator kickback, creating
glitches at the input and reference taps,
which, because of the different impedances
seen, may lead to evaluation errors.
Finally, the difference in the input
referred offset [7] among the comparators
results in additional nonlinearity.
The flash accuracy-speed-power
limits' derivation starts with its total
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
47
P ,F samp is given by the following generalized
expression:
PV NTCf C
V
FF sS
$ {
,,
sup
samp $$ $
^h .
= DD
DD
CS
$ j samp
(2)
f
is the sampling capacitance,
NTC depicts the number of settling
time constants,
portion of the total period /f1 s
sig DD
jF ,samp captures the
allocated
to sampling, and sup{ is a
supply use percentage (/ ).VV
the same way, P ,F comp , modeling the
In
comparator as a two-stage integrator-latch,
is found as
/, with CL being ,, ; "
comp = DD j comp
++
'6^h
2
L
lnBER-1@$$
PV
fC V
BA
C
FF sI I
I
$$ $$
$
2
T
logln2
VGT 1E .
(3)
The first pair of the curly brackets
includes the contribution of the
noise-critical input integrator with
,
A -gainI
tains the metastability-critical
ou Im,Ls L
tincomp
= $$
,,
the /f1-period fraction occupied by
gI V
s
the comparator. Allocating a portion
of a total noise budget to the above
expressions, [3] determines
and C ,L
C ,S
C ,I
leading to fundamental limits
imposed by physical quantities.
In fact, the process used puts a lower
mL, LGT [6]. jF ,comp
j $$
CC
while the second pair conlatch
contribution
[via BER] from its input/output
exponential regeneration
{/(
captures
VA expVg fC )},
and the basic MOS equation linking
II
gmI
,tot
=+
CC
LL gmL
,tot
=+
,
,I
PP
FF
,,
totsampcomp
laddig
=+ $++
^h
21
PF,
B
PP .
FF
,,
(1)
limit to the value of these capacitances
through minimum realizable gate sizing,
which we denote as
C .min Further,
the comparator input capacitive load,
C ,,Iin
erable power overhead. C ,Iin
to the process, f ;T
fT .
gmI
,
the speed, f ;s
via the following expressions:
,
2rCin,I
gmI
,
2rAC
II
,comp $ f ,
2r
CA C cm (5)
in .,II I
,comp $ f
$
jFs
rfT
,
where (5) results from dividing (4a)
by (4b), f
bw,I denotes the comparator
input integrator bandwidth (100%
slewing), and a 2× overestimation is
included to capture practical overhead
(e.g., interconnect). Similarly, the parasitic
loading at the output of each block
is considered, taking into account its
process,
f ,T for a given biasing (),VGT
the parasitic loading at the output of
each block is considered
gC$,,
,
mI I par
. CI +
gC$,,
,
mL L par
gmI
rfT
,
,
. CL +
gmL
rfT
,
(6a)
.
(6b)
Incorporating all the above to (2)
and (3), P ,F samp and P ,F comp
assume
their complete forms as in (7) and (8)
shown at the bottom of this page
PV NTCf
CC
AC
FF s
S
,,$ j samp
B
samp = DD
"
'
,
II c
$
min, 21
,comp $ f
^
jFs
rfT
$ ^{supVDDh.
+- h
$$ $
$
;
max
max
m,Cmin1E
(7)
bw . jFs
Z
[
\
]]
]
(4b)
and CI
(4a)
to the sampler imposes a considis
related
PV fFF s,, >* 1 - 2 V Fsj comp $ f 4
min, T
comp = DD j comp
+
Z
[
\
]
]
]]
$$ $
BA 2
2
h
1 -
6^ -+ @ max " CC VGT
6^ -+ @ jFs
loglnlnBER-1
Ih $
BA 2
r
2IL min,
loglnlnBER-1
,
$
,comp $ f
fT
$$ $
T
max " CC V
,
$
,
rV
GT
I
$
fT
2
_
`
a
b
b
bb
V
X
W
W
W
WW
.
(8)
II

IEEE Solid-States Circuits Magazine - Winter 2022

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