IEEE Solid-States Circuits Magazine - Winter 2022 - 49

for mre ,f which is reasonable for a
class-AB circuit. To give a baseline
for
S,dig
P , of each bit, a total of five
gates is assumed, three for control,
one for clocking, and one for storing,
leading to
PV fB CV5,minSs
dig = $$ $$$
DD
DD
.
(15)
Pipeline Accuracy-Speed-
Power Limits
One of the most popular architectures
to realize high resolution and
high speed is the pipeline ADC [11],
[12], (Figure 4). It incorporates a cascade
of m-stages with B -bitss
(),sm B
each
= 1f 1 containing an S/H,
a flash sub-ADC, a sub-DAC, and a
residue-amplifier (RA) with A -gains
to amplify the difference at the summing
node,
may be allocated a valthe
precision requirements on each
stage RA; however, this leads to an
increased flash sub-ADC loading, inducing
a power burden when pushing
the speed.
Although more hardware efficient
than the flash and faster than the
SAR,
the pipeline's main limitation
is the requirement for accurate RA,
with stringent speed, noise, linearity,
and power requirements. Open-loop
amplifiers [12] or integrators [14]
have been adopted, resulting in power
savings, given that the overhead of
the necessary error correction does
not overcome these savings. The
pipeline latency also poses an issue
in feedback systems.
The pipeline accuracy-speed-
V .res The sub-DAC and RA
combination, known as the multiplying-DAC,
provides the input to the
next stage. As
ue, 2 ,Bs
which conveniently matches
the range of each stage with its back
end but does not allow any margin to
absorb sub-ADC errors. Redundancy
is often incorporated by making As
smaller than
2 ,Bs with 2B 1sbeing
a
common value, and using the remaining
range for error absorption. Consecutive
stages operate in opposite
clock phases, and the overall pipeline
outputs a total BB BBm
=+ g12++
bits. The digital logic combines the
bits in a weighted sum fashion and
generates a new output with a latency
of m clock periods. Pipelining allows
for an increased throughput bound by
the speed of only one stage, enabling
very high speed. Unlike flash ADCs,
there is a linear, rather than exponential,
increase in hardware with B.
Two key design considerations
are stage scaling and B .s Although
many options exist, an optimum
scaling factor of roughly /A1 s
is
common, and its supporting analysis
is presented by [13]. Regarding ,Bs
reducing it allows for a faster multiplying-DAC
settling and a lower flash
sub-ADC loading, but this comes at
the expense of more pipeline stages.
On the contrary, increasing Bs
duces the stage count and relaxes
reFIGURE
4: A B-bit m-stage pipeline ADC.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
49
Vin
Stage-1
B1
Stage-2
B2
power limits start by considering
B -bits
s -= ,, ,).
stages including 2×-redundancy,
resulting in Bs -1 effective
bits (B 11 23 4 The optimum
scaling factor /A1 s
ever, stopping at the process C ,min
and the m-stages are determined
by adding Bs
#
bits to the last stage
to realize the total resolution, B. An
S/H-less input is assumed. Including
sampler, RA, comparator, ladder, and
logic contributions along the entire
pipeline, the power of a
Bs-bit /stage
m-stage is generally expressed as
PP P
Pm PP
PP P
$
,, ,,
,, ,,
totsampRAtot
comp totlad
=+ +++^
^h
21s
B
PP
P digh .
$
(16)
For P ,,P RA tot
g C,
the
basic open-loop
m,RA RA amplifier is considered [2],
with a gain of 2B 1sand
purely linear
settling to ¼ LSB accuracy of the back
S/H2
ADC2
Vsh2
DAC2
+
-
VDAC2
B2
Stage-3
B3
Stage-m
Bm
Align and Combine (B1 + B2/Ad1 + B3/Ad1∗Ad2+ ... +Bm/pAd(1:m-1))
B
Dout
PV I
V
P,RA,tot
=
=
DD
DD
hlin
,
$
RA,tot
$$ .
2
g
m,RA,tot
VGT
(18)
For P ,P samp all the previous loading
and process contributions are
included with the addition of the RA
input loading to the sampler
C ,,in RA
Vres
A2
1- /f periods
is assumed, howend
at a percentage, gset , of the RA
time. The contribution of all the RAs
along the pipeline is factored by considering
the CRA
asymptotic expansion
[3], including stage scaling. The
same holds for the sub-flash comparators,
C
,,Iin
with the appropriate /f1-periods
tion, jP,comp , in the pipeline. Including
is found as
loading the RA, given by (5)
fracall
loading and process effects at the
RA output, g ,m RA
gA f
A
ms
,,
$
BBs 12 2hh ln
^^
^
1- s $
-
-- +
r
RA
-
RA tot = $$ s
gset
j RAP,
^ -- + $$max " CCmin,
BBs 12 2hh ln
RA
$
$
#$2-i=0
^Bi
s
1h$
,
,
j RA $f
gset $fT
,
= / max " CCmin,
m 2
+- $$ ,.
i=0
^ ss1h$
B
in 2-,I
21h
/ max " CCmin,G
m 2
^Bi
(17)
In the above, jP ,RA captures the
fraction given to the RA.
In a typical pipeline, the RA shares
half of the period with the sub-flash
(about 70% of ./ ),f05 s
and part of that
time (commonly 50%) is allocated to
gset . CRA
noise similar to the sampler and comparator.
With a final addition to the
g ,,m RA tot
of a linearity factor, h n #li 1 ,
as in [2], to capture the overhead for a
sufficient precision to drive the back
end, P ,P RA,tot
is written as
is determined for a given RA
Ps
A2Vres
IEEE Solid-States Circuits Magazine - Winter 2022

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