IEEE Solid-States Circuits Magazine - Winter 2022 - 67

processing, large-memory recommendation
systems, and spike-based
neuromorphic processing.
It is important to note that the metrics
that matter at the system level
are energy/inference (or per training
example) and inferences/s (or training
examples/s) on a specific task at
a given inference (or final trained)
accuracy. This year's submissions
significantly push the state of the art
of these efficiency and throughput
numbers yet again, often by combining
multiple enhancement techniques
within a single chip (or multiple
chiplets), implemented across a broad
range of technology nodes (Figure 25),
as in the following:
1) CIM architectures continue to be
popular, making use of SRAM,
dynamic-capacitive, and even
Flash-based memories.
Innovations
here continue to shift toward
supporting more complicated
and larger network models
and increased flexibility through
the inclusion of digital blocks at
the edge of CIM macros.
2) The exploitation of sparsity in
various forms has long been an
important focus of both inference
and training acceleration for imaging
applications, given the large
number of zero activations and
zero weights within deep convolutional
neural networks. The advent
of transformer networks has
introduced the need for sparsity
within attention-based computing
since the number of operations
can scale as rapidly as the square
of the sequence length.
3) The incorporation of analog circuitry,
either at the front end of
the network or to perform multiply-accumulate
operations in either
the current or charge domain
by using Kirchhoff's current law,
was featured by several papers,
leading to better energy efficiency
while maintaining reasonable
neural network accuracy.
4) In contrast, several papers explicitly
chose to avoid analog accumulation,
preferring the precision of a
pure digital solution for CIM, spike
accumulation, and other computational
tasks, exploiting sparsity
and data reuse to achieve improvements
in energy efficiency. Figure
26 helps describe this taxonomy
between digital, analog, OFF-memory,
and IN-memory computing.
5) While most submissions focus on
the inference of imaging workloads
by using convolutional
neural networks, particularly
for low-power, edge-based computing,
several papers focused
on nonimaging workloads. For
transformer networks, papers
focused on the efficient computation
of the attention-based
compute; for recommendation
systems, hybrid bonding was introduced
to reduce the latency
and energy costs of accessing
dynamic RAM (DRAM). A novel
Implementation
Mixed Signal
Custom Signal
Synthesized All-Digital
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(a)
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Type Fmax (GHz)
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PLL
MDLL
ILCM
FLL
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Reference
Fractional
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(b)
FIGURE 24: (a) The key digital clock generator FoM in recent years, defined as: FoMr = 10 ×
log10 {(JitterRMS/1 s)2 × (Power/1 mW) × (fref/50 MHz)}. (b) The spur reduction trends.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
67
Spur Magnitude With Respect to Carrier (dBc)
FOMr (dB)
IEEE Solid-States Circuits Magazine - Winter 2022

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