IEEE Solid-States Circuits Magazine - Winter 2022 - 69

of operations/s and energy/operation
is not particularly apparent. Yet,
ISSCC attendees should keep in mind
that these tera operations per second
(TOPS)/W and TOPS/s specifications
depend strongly on the level of integration
of a chip and the particular
neural network topologies being used.
At ISSCC, we see a clear trend toward
more complete SoC integration in
which the highly efficient media access
control (MAC) compute arrays
introduced during the past years are
now integrated into full processing
systems. A second trend is the support
for larger and more complex
networks. Going forward, as the field
matures, we believe that a common
benchmarking methodology must be
established that can properly account
for the application context and provide
proper translation between lowlevel
and system-level performance
metrics [1]. In the meantime, the clever
combination of sparsity, variable
precision, and in-memory computing
technologies is continuing to enhance
deep learning processor efficiency
and throughput. With the increase of
system-level integration of machine
learning engines together with important
subsystems (imaging chips, image
preprocessing, audio filtering and
preprocessing, and so on), these performance
improvements will continue
to open new AI applications.
Memory
Subcommittee Chair: Jonathan
Chang, TSMC, Hsinchu, Taiwan
The demand for high-density, highbandwidth,
and low-energy memory
systems continues to grow everywhere,
from HPC to SoC, wearables, and the
IoT. This year, the conference presents
a high-bandwidth, 16-Gb, 27-Gb/s/pin
GDDR6 DRAM and 192-Gb, 12-high,
896-GB/s HBM3 DRAM. CIM performance
and energy efficiency are improved
by a SLC-MLC, pulse-code modulation
(PCM) CIM macro that achieves 20.5-
65 TOPS/W. The highest densities per
area are reported for 3D-NAND in TLC
and QLC NANDs, both adopting a circuit-undercell-array
structure while
boosting programming throughput.
Top Papers From ISSCC 2022
■ " A 1-ynm, 1.25-V, 8-Gb, 16-Gb/s/
pin, GDDR6-Based Accelerator-inMemory
Supporting 1-TFLOPS MAC
Operation and Various Activation
Functions for Deep Learning "
■ " A 40-nm, 2M-Cell, 8b-Precision
Hybrid SLC-MLC PCM Computingin-Memory
Macro With 20.5-65.0
TOPS/W for Tiny AI Edge Devices "
■ " A 192-Gb, 12-High, 896-GB/s HBM3
DRAM with a TSV Auto-Calibration
Scheme and Machine-Learning
Based Layout Optimization "
■ " A 16-Gb, 27-Gb/s/pin, T-coil-based
GDDR6 DRAM With Merged-MUX
Tx, Optimized WCK Operation, and
Alternative-Data-Bus "
■ " A 1-Tb, 4b/Cell, 4-Plane, 3D Flash
With 162-Layer, 68-mm2
and 2.4-Gbps IO Speed "
Chip Size
CIM
CIM solutions aim to impact next-generation
data centers and cloud inference
and training applications, with
the goal of substantially reducing energy
consumption and the total cost of
ownership. Edge device inference and
training are rapidly increasing, with
a variety of applications spanning autonomous
driving, driver assistance,
image recognition, voice recognition,
and surveillance. CIM solutions focus
on enabling increased performance
and capacity on edge devices, supporting
new applications and improved
performance for end users.
1.E+04
1.E+01
1.E+03
1.E+00
1.E+02
1.E-01
1.E+01
1.E-02
1.E+00
1.E-01
2015 2016 2017 2018 2019
Year
(a)
16 bit 8 bit 4 bit 2 bit Binary/Ternary
FIGURE 28: The evolution in (a) the energy efficiency and (b) the throughput per unit area of machine learning inferencing processors.
IEEE SOLID-STATE CIRCUITS MAGAZINE WINTER 2022
69
2020 2021 2022 2023
1.E-03
2015 2016 2017 2018 2019
Year
(b)
2020 2021 2022 2023
Maximum TOPS/W at Emin
Maximum TOPS/mmm2 at VMAX
IEEE Solid-States Circuits Magazine - Winter 2022

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