IEEE Solid-States Circuits Magazine - Winter 2022 - 70

High-Bandwidth and
Low-Power DRAM
To keep pace with the ever-increasing
performance requirements of various
applications, from graphics/mobile
to supercomputing, DRAM continues
to scale in density, form factor,
and bandwidth. ISSCC 2022 includes
benchmarks for the latest interface
standards, such as 896-GB/s HBM3
for the highest-performance applications
(HPC and AI) and a 27-Gb/s/
pin GDDR6 for graphics applications.
Figure 29 illustrates the DRAM bandwidth
growth over the past 14 years.
Nonvolatile Memory
In the past decade, a significant investment
has been made in emerging
memories to find an alternative to
floating gate-based nonvolatile memory
(NVM). Emerging NVMs, such as
phase-change memory (PCM), ferroelectric
RAM (FeRAM), magnetic spin
torque transfer, and RRAM, are showing
potential to achieve high-cycling
capability and lower power-per-bit
read/write operations. However,
conventional flash memories are
continuously improving, confirming
them as the mainstream today and
into the near future.
This year's papers report improvements
in the write performance for
conventional 3D flash memory TLC
(164 MB/s) and QLC (60 MB/s) and the
widespread acceptance of asynchronous
page read for read performance.
They also report improvements in the
bit density for TLC (.
11 55Gb/mm)2
1,000
100
HBM(x)
GDDR(x)
LPDDR(x)
10
DDR(x)
1
2008 2010 2012 2014
2016 2018 2020 2022
Year
FIGURE 29: The DRAM data bandwidth growth. WIO: wide-I/O.
10,000,000
1,000,000
100,000
10,000
1,000
100
10
1
DDR3
DDR4
DDR5
GDDR3
GDDR5
GDDR6
LPDDR2
LPDDR3
LPDDR4
LPDDR5
WIO2
HBM
HBM2
HBM3
and QLC (15Gb/mm ).2
These high
densities are achieved through advancements
in 3D architectures with
more than 220 stacked-wordline
(WL). Figure 30 conveys NVM capacity
trends.
NAND Flash Memory
NAND flash memory continues to advance
toward having a higher density,
lower power, and higher performance,
resulting in low-cost storage solutions
that are replacing traditional magnetic
hard disk storage with solid-state
disks. 3D memory technology is the
mainstream for NAND flash memory
in mass production by semiconductor
industries. Periphery under the array
is currently the reference architecture
for TLC and QLC: it is enabling a
higher bit density and multiple planes
for throughput improvement. Stateof-the-art
for TLC uses more than
220-stacked-WL. This year, emphasis
is on the current-steering logic noisecanceling
scheme and IO speed improvement
(up to 2.4 Gb/s) through
a continuous-time linear equalizerbased
Rx and an internal reference
voltage generator. One paper related
to QLC reports the highest bit density
of 15Gb/mm,2
with 162-stacked-WL
and 60 MB/s for program throughput.
Figure 31 relays the observed trend in
NAND Flash capacities at ISSCC over
the past 20 years.
Innovative Topics: Medical
Cond. 1 Mb
ISSC, VLSI Circuits,
NAND Flash
ASSCC, IEDM, VLSI Technology
8 Gb
PCM
FeRAM
MRAM
2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 20202022
Year
FIGURE 30: The NVM storage capacity (in megabits) trend. ASSCC: IEEE Asian Solid-State
Circuits Conference; IEDM: IEEE International Electron Devices Meeting.
70 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
428 Mb
32 Gb
RRAM
1.33 Tb
1 Tb
Subcommittee Chair: Chris Van
Hoof, IMEC, Leuven, Belgium
As illustrated at ISSCC 2022, biomedical
systems that interface with the body
and the brain in wearable, implantable,
and in vitro applications continue to
evolve toward more robust, functionally
complex, and energy-efficient solutions,
as well as closed-loop operation.
Wearable and implantable SoCs record
weak biological signals in the presence
of real-life interference, under stringent
power and size constraints. These
new SoCs and corresponding wireless
power/data transfer techniques pave
the way toward robust microdevices
that enable innovations in health
Data Bandwidth (GB/s)
IEEE Solid-States Circuits Magazine - Winter 2022

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Winter 2022
