IEEE Power Electronics Magazine - March 2020 - 22

practical limitation for the number of MOSFETs in paralwithout facing significant voltage drop. An external capacilel is eliminated, and a large number of MOSFETs can be
tor with a value of 100-200 times the input capacitor (C iss) of
connected in parallel to achieve a very high-current device.
the MOSFET would be proper for this purpose. Also based
Due to similar values of inductances added to drain
on various simulations/experiments, it is concluded that an
and source of the MOSFETs in Figure 1(a), the dynamic
R G of around 10-20 Ω works well for the proposed circuit of
currents can be well balanced (as
Figure 1(b). If chosen smaller, R G may
proven later via simulations and
not be able to suppress the possible
ex per iments). However, because
resonance between C G and L G and
The CG must be selectthe source inductances of parallel
avoid dc/lower-frequency circulating
ed with a high-enough
MOSFETs are not of the same size,
current components. However, if the
during the switching transients the
value of the selected R G is too large,
value to be able to
voltage drop across the parasitic
it will block the charging current to
provide the gate power
inductance will be different for adjaC G and limit the operating switchcent MOSFETs. This can cause ciring
frequency.
during the switching
culating currents in the gate-source
In Figure 1(b), for each of the
event without facing
path of the MOSFETs, deteriorating
positive/negative gate-driving voltboth gate-source voltage and drainages, the charging path is composed
significant voltage
source voltage waveforms of the
of 2 # R G resista nce a nd 2 # L G
drop.
MOSFETs [Figure 1(a)]. Between the
inductance. Charging current can
two aforementioned impacts, ringflow through the charging path at
ing added to the gate-source voltage
all times, whereas discharging only
of the MOSFETs can be of more severe impact, causing
happens at switching moments. Assuming that the voltdelayed switching or damaging the gate structure of
age across the capacitor C G always remains within 5%
the MOSFETs.
of its nominal value (±2.5%), the power delivered to the
A practical way to stop the circulating current in
capacitor via the charging path is calculated from
Figure 1(a) is by using isolated dc-dc converters for individual MOSFETs to provide their gate-driving power. The
^VGi - 0.975 # VGi h

Pcharge =
# 0.975 # VGi .(1)
2 # RG
galvanic isolation of the dc-dc converter would be a barrier against the circulating current components in Figure
1(a) via the gate path. However, this would come at a high
In (1), the effect of L G is neglected during charging,
and unreasonable cost, because typically the isolated dc-
because the charging current is a dc component. In addition,
dc converters are more expensive than a discrete MOSFET
the capacitor voltage is considered to be at its minimum
itself. Considering the high-frequency nature of the circulat(worst case, which happens at the maximum switching freing currents in Figure 1(a) and the fact that a large inductor
quency). However, the discharging component of power for
can provide a high impedance for high-frequency current
C G is equal to the gate power of the MOSFET, which can be
components, as part of the proposed method an RL circuit
calculated from (2). In this equation, the static power losses
is used to decouple the gate-driving power of individual
in the gate-driver circuit are neglected:
MOSFETs from the high-frequency ringing point of view.
Figure 1(b) shows a low-cost impedance-based decou
Pdischarge = VGi # fSW # Q G, (2)
pling system for gate power of each individual MOSFET
to avoid the circulating currents. In this figure, VGP and
where Q G is the gate charge of the MOSFET, and fSW is
the switching frequency. To maintain the voltage stabilVGN are the positive and negative gate-driving voltages,
ity across C G, the charging power must be greater than
respectively. An inductance L G (to suppress the highor
equal to the discharging power. This will yield the folfrequency ringing voltage caused by switching event on
lowing
equation for the maximum switching frequency
L Si) is added in series with a resistance R G (to suppress
in
terms
of either one of the positive/negative gate-drivthe lower-frequency components and avoid possible resoing voltages:
nance between L G and C G) . In addition, two capacitors
C G are added after the RL networks to store the energy
0.02 # VGi
required for switching of the MOSFETs. C G capacitors

fSW # 2 # R # Q
.(3)
G
G
will be charged during the on/off state of the MOSFETs
and will be discharged during switching transients. The
Note than (3) must be held valid for both VGP and VGN .
RL network will allow charge of the capacitors at a slow
Also, a safety factor must be considered for the switching
rate but will block the instantaneous high-frequency cirfrequency calculated from (3), to take into account the
culating currents from flowing.
static power dissipation in the gate-driver stage.
The C G must be selected with a high-enough value to be
As another criterion, when designing the circuit shown
in
Figure
1(b), the inductance L G must be selected such
able to provide the gate power during the switching event

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z March 2020

IEEE Power Electronics Magazine - March 2020

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