IEEE Power Electronics Magazine - March 2020 - 23

networks are used to decouple the gate-driving voltages of
that it will limit the circulating current components. The
individual MOSFETs, where a 20-Ω resistor is connected in
value of circulating currents will depend on the value of
series with a 10-nH, 1.1-A inductance. The MOSFETs under
inductances added in series with the source terminal of the
MOSFET as well as the MOSFET's di/dt
test are IXFX90N30 from IXYS, with
rate. Once the magnitude and fre300-V 90-A voltage and current ratquency of the most extreme ringing
ings. A totem-pole bipolar junction
The value of circulatvoltages across the parasitic inductransistor (BJT)-based gate driver is
tances [V1 and Vn in Figure 1(a)] have
used for each individual MOSFET, and
ing currents will
the gate signal is isolated by means of
been calculated, the inductor value
depend on the value
an optocoupler. Finally, yet imporcan be selected to limit the current
tantly, the MOSFETs are driven with
to low magnitudes at all frequencies.
of inductances added
10-Ω gate resistances. The maximum
A circulating current in the order of
in series with the
switching frequency feasible for the
a few 10s of milliamps or lower will
source terminal of
simulated system is calculated from
guarantee clean switching wave(3) to be around 2.7 kHz, to ensure the
forms. Special attention must be paid
the MOSFET.
stability of VGN .
to the current rating of the inductor, such that it does not saturate
Figure 3(a) and (b) demonstrates
under the worst circulating current
the turn-on and turn-off waveforms of
scenario. Typically, off-the-shelf inductors in 2512 or 1812
the paralleled MOSFETs. In this figure, VDS1, VDS2, and VDS3
surface-mount device packages are well suited to serve in
are the drain to source voltages of Q 1, Q 2, and Q 3, respecthe proposed circuit.
tively. The same order is valid for the currents, where I D1,
Other than the gate power path, the gate signal path
I D2, and I D3 are the drain currents for Q 1, Q 2, and Q 3 . Figcan also propagate the circulating current i circ shown
ure 3(a) shows that during the turn-on transient, the drain
currents rise with the same slope and overlap each other.
in Figure 1(a). Thus, the gate command signal also
In a like fashion, the drain-source voltages of the paralneeds to be isolated for MOSFETs in parallel. The most
leled MOSFETs change quite similarly, which will guarpractical method for implementing this feature is to use
antee comparable stress and switching loss for all of the
an optocoupler-based gate-driver chip for individual
MOSFETs during turn-on. Figure 3(b) shows the turn-off
MOSFETs, which costs a fraction of what the MOSFET
waveforms where the rising slope of drain-source voltages
does and provides galvanic isolation for the gate commatch perfectly. Also, the drain currents change with the
mand signal.
same slope, guaranteeing similar a turn-off process for
The configuration proposed in Figure 1 enables the parall MOSFETs. The waveforms shown in Figure 3 are capalleling of a large number of MOSFETs that can be laid in
tured using devices with completely matched parameters,
linear configuration and yet share the dynamic switching
to merely show the effect of mismatched inductors at the
currents nearly perfectly equally. The next sections will
drain/source of the devices (while their summation stays
provide simulation and experimental results to prove the
constant) on the switching waveforms.
validity of the proposed approach.
To evaluate the effectiveness of the decoupling circuit
proposed
in Figure 1(b), the same circuit (Figure 2) is simuSimulation Results
lated
one
more
time. This time the impedance-based decouA system composed of three MOSFETs in parallel is
pling circuit is removed, and the totem-pole BJT-based gate
selected for simulation study. Simulations are carried out in
drivers of the paralleled MOSFETs are directly connected
an LTspice environment, and Figure 2 demonstrates the systo the same +10/-2-V supply bus. Also, the gate signal is
tem and the values of the inductances added in series with
directly fed to the base of the BJTs without optic isolation.
the drain and source terminals of the individual MOSFETs.
Although 80 nH of total parasitic inductance added in series
with a MOSFET may seem to be a large value for just three
devices, selection of this value demonstrates that under
excess mismatch in drain/source inductances between the
10 nH LD 1 40 nH LD 2 70 nH LD 3
paralleled MOSFETs, the proposed method can be used to
balance the peak switching currents (and thus, the voltage
Q1
Q2
Q3
100 A
stresses) among paralleled MOSFETs. This will enable parallel connection of a large number of MOSFETs in a linear
(or other) layout.
70 nH LS 1 40 nH LS 2 10 nH LS 3
The gate-driving voltages in simulation are all provided
by a single 12-V power supply, suppling +10/-2 V for the on/
off state of the devices, respectively. However, in a similar
FIG 2 The simulated circuit with three MOSFETs in parallel to
fashion to the circuit shown in Figure 1(b), RL impedance
the switch 100-A current.

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