IEEE Power Electronics Magazine - March 2020 - 25

Drain-Source Voltages (V)
Drain Currents (A)

200

VDS1
VDS2
VDS3

150
100
50
0
0.100025
40

0.10003

0.100035

0.10004

0.100045

0.10005

0.100055

0.10006

30
20

ID1
ID2
ID3

10
0
-10
0.100025

0.10003

0.100035

0.10004

0.100045
Time (s)

0.10005

0.100055

0.10006

FIG 4 The turn-on waveforms corresponding to Q 1, Q 2, and Q 3 MOSFETs under 100-A load current when the impedance-based
decoupling circuits of Figure 1(b) and the optocouplers of the gate-driving stage are removed from the system.

The shunt resistors are in a 2512 package, and two resistors
are paralleled per switch position to ensure minimal impact
on parasitic inductances of the path. For each MOSFET, a
separate gate-driver integrated circuit (SI8261 from Silicon
Labs) with optical isolation of signal is used. A 12-V gatedriving voltage is supplied to the board and is converted
into +10/-2-V gate-driving voltages. Also, an RLC network
similar to the circuit shown in Figure 1(b) is used for each
MOSFET to provide its decoupled gate power.
Once the printed circuit board (PCB) is designed, several iterations have been made to achieve parasitic inductances similar to those shown in Figure 2. For this purpose,
the PCB was extracted to EMWorks software, and trace
inductances were calculated. After several iterations, parasitic inductances very close to the numbers shown in Figure 2 were achieved, and later, measurements on the manufactured PCB validated the conducted calculations in the
EMWorks environment.
Figure 5 shows the designed PCB, on which the values
for parasitic inductances are marked. The devices are oriented in a linear form, which allows paralleling a large number of MOSFETs. The gaps among the individual MOSFETs
are used to match the parasitic inductance values shown
in Figure 2 and create fairly large mismatch in inductance
values in series with the drain and source pins of the MOSFETs, to observe performance of the proposed approach
under large variation in values of L D and L s of different MOSFETs.
Figure 6(a) and (b) demonstrates the turn-on waveforms
of the MOSFETs under a 9-A load current. In a similar
fashion to the simulation results, the experimental currents and voltages match very well with each other. This
ensures product reliability and similar rate of aging for the
MOSFETs in parallel. In Figure 6, the high-current spike at

turn-on is due to the much higher current capacity of the
devices under test (compared to the test current), which
brings about large output capacitance for the MOSFETs. In
this way, the discharging current of device C oss at turn-on is
larger than the actual conducted load current [7].
Similarly, the turn-off current waveforms of the board
are captured and shown in Figure 7. Due to slower rate of
VDS rise for the MOSFETs (due to the power supply's slow
transient response), the drain-source voltages are excluded
from this figure.
Figures 6 and 7 provide experimental proof for validity
of the proposed paralleling technique. As demonstrated in
these figures, the switching waveforms of the paralleled
MOSFETs match each other during turn-on and turn-off
events. Also, using the proposed method, current sharing
is achieved from the very first switching transient. The only
drawback of this solution is the additional switching losses
in the system due to larger inductances in switching loops,
which is not a major barrier when taking into account the
low switching frequency nature of the target application.
In Figure 5, the gaps between MOSFETs can accommodate at least six more MOSFETs. This is an indicator that

Table 1. The design/test parameters for
the implemented setup.
Parameter

Symbol

Value

Number of MOSFETs in parallel

MOSFETs under test

Q 1-Q 3

IPT020N10N3ATMA1

Test voltage

Vdc

60 V

Test current

I dc

Positive gate-driving voltage

VGP

10 V

Negative gate-driving voltage

VGN

-2 V

March 2020

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IEEE Power Electronics Magazine - March 2020

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