IEEE Power Electronics Magazine - September 2021 - 41

current and average drain voltage. Then the PCOSS
expressed as:
PV C
CDSDS
BUS
OSSOSS
= #
where the COSS
V
$
dV
^h
the drain node of the power transistor. PGD
IDS
PEX
Rp2 Lp2
G
External
Connection
Rg
Cgs
III-V HEMT Model
External
Connection
(a)
l
Rp
Lp
d
Resistivity ρ
(b)
1~3 nH
Vind = L
0.2~0.3 nH
diL
dt
S
Lp3
Rp3
IDS
Lp1
D
Rd
Cgd
Cds
Rs
Rp1
External
Connection
is
(5)
is the voltage-dependent capacitance at
occurs at
Gate charging and Gate discharging periods, which is
written as:
PV QfGD GG
= $$
where the VG is Gate driving voltage and QG
has smaller conduction resistance R ,DS
capacitor, and QG
lower P ,CON
(6)
is the
Gate charge.
It has been proved that the WBG III-V power device
input/output
than Si MOSFET [28], which leads to
P ,COSS P ,GD and better converter efficiency.
As in Figure 4, GaN HEMT has no body diode compared to
Si-NMOS devices, so reverse recovery loss could be prevented
during switching state transition.
However, inevitable parasitics of interconnections
and packaging limit the converter operation frequency
and induce voltage ringing and impedance mismatch.
Figure 5(a) shows a schematic model of a small-signal
III-V power transistor with external connections. In ON
mode, the extra power losses caused by parasitic elements
in external connections come from drain parasitic
inductor and resistor and source parasitic inductor
and resistor.
Figure 5(b) shows a simplified model of the inductor at
high frequency. Furthermore, a higher level of integration
results in lower parasitic inductances and
predicted in Figure 5(c) and contributes to smaller
voltage ringing.
III. HI-Enabled Power Converter Practices
Figure 6 shows the broad applications of chip-scale power
converter modules designed in HI technologies, including
voltage step-up/down converters and integrated power
switching modules. The key technological advancement in
recent years is aiming at three goals: converter miniaturization
through a higher level of integration, reduced converter
complexity through innovative design approaches, and better
conversion efficiency.
A. Step-Down dc-dc Converter
Eyal Aklimi [22] et al. proposed a fully-integrated
40 MHz 16-V to 1-V buck dc-dc converter chip for
15~30 pH
Table III. Comparison of monolithic and HI
enabled step-up dc-dc converter.
PCB_lines Chip_bonds
Packaging Method
(c)
FIG 5 (a) Schematic model of a small-signal III-V power transistor
with external connections; (b) Parameters and resistivity
()t of a piece of the inductor; (c) Parasitic inductance of transmission
line on PCB and bonding wire per millimeter length,
and flip-chip solder balls of 50 μm diameter.
Flip-Chip
Ref Technology VIN/VOUT POUT,MAX Freq. P&D hMAX
[21]
80V BCD
[22] MOSFET PCB
[9]
[10]
III-V/CMOSChip-to-Chip
III-V/CMOSDie-on-Die
3.3/80
12/30
12/18
3.3/70
0.35W
7W
4.16W
1.68W
200
kHz
75
MHz
300
MHz
49.5
kHz
0.045
W/mm2
0.29
W/
mm2
47.3%
70.3%
0.35
W/mm2
/
53%
87%
September 2021 z IEEE POWER ELECTRONICS MAGAZINE 41
Parasitic Inductance Level
IEEE Power Electronics Magazine - September 2021

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