IEEE Technology and Society Magazine - June 2015 - 22
information processing beyond that
attainable by scaled CMOS. Such
alternatives are numerous and best
documented and catalogued by the
ITRS [1], [2] and associated publications [3]-[5]. Since the inception of
the INC conference series, the IPWGN
working group has been chartered to
collect information on research programs, identify gaps, and stimulate
international collaboration. Understanding the scope, identifying programs and frameworks, and then
rendering useful conclusions is the
primary task of the IPWGN [6], and as
such, in the effort to disseminate this
information, this article aims to synthesize the learning, outcomes, and
conclusions from IPWGN activities.
ciples (research vectors) used by
ITRS/ERD and adopted by INC and
IPWGN in 2010 [6]. These include:
1) Computational state variables
other than electron charge [7].
2) Non-equilibrium systems [8].
3) Novel energy transfer interactions [9].
4) Nanoscale thermal management [10].
5) Beyond lithographic manufacturing processes [11].
6) Alternative architectures [12].
To complement the focus on a
digital switch, we have also included the notion of memory device
requirements (and those emerging
ideas) [13], more generally termed
here as "storage." Furthermore, we
have embraced and further refined
[14] the concept of More-than-Moore
(MtM) as initially proposed by Europe
and first introduced in the 2005 ITRS
roadmap. The "More-than-Moore"
approach allows for the non-digital
functionalities (e.g., RF communication, passive, MEMS) to migrate
from the system board level into the
IPWGN Methodology
Our first step begins by identifying
potential research gaps via composing a framework of comparison
and tabulation based on important
nanoelectronics research guiding
principles. For our task, we have
employed the original guiding prin-
System in Package (SiP) or onto the
System on Chip (SoC) [15], [16].
Figure 1 presents the relationship
between these various concepts.
Based on the IPWGN committee
agreement, our technical framework
for evaluating the most relevant
challenges have been categorized
as follows:
1) Computation and Storage
a) 0D/1D/2D charge based extended CMOS devices [17] [18]
b) Computational state variable
other than solely electron
charge [19]
c) Non-equilibrium computation [20]
d) Information Transfer [21]
e) Thermal Management [22]
f) Manufacturing [23]
g) Architectures [24] [5]
2) More-than-Moore (MtM)
a) Materials and Devices [14]
b) Manufacturing Techniques [25]
c) Architecture [26]
Once our technical domain areas
were defined, we then nominated
regional IPWGN chairs to solicit data
inputs. These chairs, along with
selected colleagues from government and the private sectors who
have their "thumb on the pulse,"
convened and objectively gauged
how research efforts are reflected
with respect to our defined technical framework, allowing for interregion data normalization. For
adequate granularity, it was decided
to select R&D programs with a minimum funding threshold of $1M.
Data was also limited to founding INC regions that were actively
engaged in the IPWGN committee.
Representation included members
from the U.S.A., Europe, and Japan.
Analysis from other regions such
as Taiwan, China, and South Korea
were not included. Absolute funding numbers were not accounted
for given that public and government agencies do not publish funding information that corroborate
Evolution of Extended CMOS
Elements
Existing Technologies
re
Moo
Than
More
Top-Down
More Moore
Bottom-Down
Bey
ond
CMO
S
Beyo
nd C
New Technologies
MOS
Extended CMOS
More
ments
re Ele
Moo
Than
Elem
ents
Beyond CMOS
Year
Figure 1. The ITRS illustration showing the relationship of concepts in the evolution of
extended CMOS. This graph clarifies the relationship between terminologies such as More
than Moore, More Moore, and Beyond CMOS. (Used with permission from ITRS ERD.)
22
IEEE Technology and Society Magazine
∕
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