IEEE Electrification Magazine - December 2013 - 53
S1
Grid
ac/dc
PFC
Converter
4.0
2.0
ZVS
Region 1
1.5
1.0
turned on with ZVS and two MoSFets are always turned
on with ZcS. the rectifier diodes are turned off with low
di/dt so that the reverse recovery losses can be minimized.
the disadvantage mainly lies in the MoSFets' high peak
currents. Figure 9(e) shows the interleaved version of
Figure 9(c), which offers benefits such as reduced current
ripple and reduced filter size. however, the number of gate
drivers, MoSFets, and transformers are doubled, and the
control scheme is more complicated.
S1
S2
ac/dc
PFC
Converter
D2
L1
D1
L1
Co
+
D3
Grid
Vbat
D2
S2
D5
+
Vbat
(d)
L1
D3
D1
L2
Co
+
D3
Grid
Vbat
C1
S1
L2
-
D2
Co
D4
C1
S1
D6
-
D4
Grid
-
S1
(c)
D1
Vbat +
(b)
S1
L1
Lo1
Lo2 Co
D1
-
D2
1.75
Figure 10. The dc voltage characteristics of an LLC converter.
D5
Grid
100 V
0.5
0.75
1
1.25 1.50
Normalized Frequency (f /fp)
(a)
D3
ZVS
Region 2
ZCS Region
0.5
0.25
-
D1
420 V
fmax
2.5
Co Vbat +
D1
fp
3.0
Grid
Lo
fmin
3.5
Battery Voltage
Normalized Gain (nVo /Vdc)
between the gate signals of S1 and S2 and the gate signals
of S3 and S4. By controlling this phase difference, the output
voltage can be regulated. the advantages lie in its pulsewidth modulation (pWM) operation and wide output voltage range. however, in light load conditions, two MoSFets
in the lagging leg lose ZVS features. in addition, because of
high di/dt, there are reverse recovery losses in rectifier
diodes. Figure 9(b) is a full-bridge trailing-edge ZVS converter, which is a derivative of the phase-shift ZVS converter.
the difference between a full-bridge trailing-edge ZVS converter and a phase-shift ZVS converter mainly lies in the
switch pattern. S2 and S4 are driven by two complementary
50% duty cycle gate signals, whereas S1 and S3 are driven by
two 180° phase difference and adjustable duty cycle gate
signals. By controlling this duty cycle, the output voltage
can be regulated. the features of the full-bridge trailingedge ZVS converter are similar to those of the full-bridge
phase shifted ZVS converter. an additional clamp network
consisting of DC, RC, and CC is needed to clamp the voltage
ringing due to diode junction capacitance with the leakage
inductance of the transformer.
Figure 9(c) shows a full-bridge ZVS converter with a
capacitive output filter. the switching pattern is the same
as that of the trailing-edge ZVS converter. however, there
is no clamp network, and the output filter consists of a
capacitor. in this topology, two MoSFets are always
D4
D2
(e)
Co
-
Vbat
+
D4
(f)
Figure 11. The unidirectional nonisolated PEV battery chargers: (a) a two-stage buck, (b) a two-stage interleaved buck, (c) a buck-boost PFC,
(d) a noninverting buck-boost PFC, (e) an SEPIC PFC, and (f) a Cúk PFC.
IEEE Electrific ation Magazine / d ec em be r 2 0 1 3
53
Table of Contents for the Digital Edition of IEEE Electrification Magazine - December 2013
IEEE Electrification Magazine - December 2013 - Cover1
IEEE Electrification Magazine - December 2013 - Cover2
IEEE Electrification Magazine - December 2013 - 1
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https://www.nxtbook.com/nxtbooks/pes/electrification_december2021
https://www.nxtbook.com/nxtbooks/pes/electrification_september2021
https://www.nxtbook.com/nxtbooks/pes/electrification_june2021
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https://www.nxtbook.com/nxtbooks/pes/electrification_september2019
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https://www.nxtbook.com/nxtbooks/pes/electrification_september2018
https://www.nxtbook.com/nxtbooks/pes/electrification_june2018
https://www.nxtbook.com/nxtbooks/pes/electrification_december2017
https://www.nxtbook.com/nxtbooks/pes/electrification_september2017
https://www.nxtbook.com/nxtbooks/pes/electrification_march2018
https://www.nxtbook.com/nxtbooks/pes/electrification_june2017
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