x2 x2n x1 x1n t0 x1 x1n RoC2 t t t0 H1 t t0 H2 x2 x2n RoC1 t t0 H2 H1 IC IC p pf p0 p pf p0 t t0 t t0 (a) x1 x1n x2 x2n RoC1 t0 x1 x1n RoC2 t t t0 x2 x2n RoC1 t t0 HV HV H2 H1 H2 H1 IC IC p pf p0 p pf p0 t t0 x1 x1n x1 x1n RoC2 t x2 x2n RoC1 t t0 t t0 (b) x2 x2n RoC1 t0 t t0 t t0 RoC2 t0 HV t HV H1 H2 H1 H2 IC IC p pf p0 p pf p0 t t0 x1 x1n x2 x2n RoC1 t t0 t t0 RoC2 t t0 HV H1 H2 IC p pf p0 p p0 pf t0 t t0 (c) t Figure 11. Diagrams and graphs showing dynamic response under load power perturbations of grids connected by ICs with IE techniques. (a) No emulation of inertia, (b) emulation of inertia on the secondary side of the IC, and (c) emulation of inertia on both sides of the IC. The arrows indicate the flow of energy. IEEE Elec trific ation Magazine / D EC EM BE R 2 0 1 9 67